From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 99A5CA00C2; Thu, 13 Oct 2022 10:48:10 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A3D1942DCC; Thu, 13 Oct 2022 10:48:02 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id 5498E42DCE for ; Thu, 13 Oct 2022 10:48:00 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665650880; x=1697186880; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=iFn7ZgvBWvVTbjmU0tlrEcXLChJUR0Hu5B2rj3qBl58=; b=Md2ifLxI0gqwCFvzXul7k5HhyaqYuAuGmHGiaQWnFnww8MJSf+ZR0+1u Bw7+OImx8+Xw5f03UavyXMinzztBc9ZH4FbBDUOHw4zs6IStU18GnHlSA V3o8420h25dt1RX4q4pIM59pnqz67hDdAQHcXTUC0FELLru2s4LoEoRlC XDy4pzQmSn0mgIqOoHyJimfF8nwycM7anWbZRTrOx0TcM+Z7pNIBsYdEy GKYfZf2wzwQ+nmrBD9OknJPxXTEwRGYcjV+NOLzRhGCLarEwzM9Rb2KxW HOen1Cz77opIBKEDBcZjBOE7eLBBRecyN0Xf3zugRj9JCToW7wjKZH2xM Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10498"; a="288292699" X-IronPort-AV: E=Sophos;i="5.95,180,1661842800"; d="scan'208";a="288292699" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2022 01:48:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10498"; a="658100435" X-IronPort-AV: E=Sophos;i="5.95,180,1661842800"; d="scan'208";a="658100435" Received: from dpdk-dipei.sh.intel.com ([10.67.110.251]) by orsmga008.jf.intel.com with ESMTP; 13 Oct 2022 01:47:58 -0700 From: Andy Pei To: dev@dpdk.org Cc: chenbo.xia@intel.com, rosen.xu@intel.com, wei.huang@intel.com, gang.cao@intel.com, maxime.coquelin@redhat.com Subject: [PATCH v4 4/8] vdpa/ifc: write queue count to MQ register Date: Thu, 13 Oct 2022 16:44:30 +0800 Message-Id: <1665650674-291949-5-git-send-email-andy.pei@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1665650674-291949-1-git-send-email-andy.pei@intel.com> References: <1661229305-240952-2-git-send-email-andy.pei@intel.com> <1665650674-291949-1-git-send-email-andy.pei@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Write queue count to IFCVF_MQ_OFFSET register to enable multi-queue feature. Signed-off-by: Andy Pei Signed-off-by: Huang Wei --- drivers/vdpa/ifc/base/ifcvf.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/vdpa/ifc/base/ifcvf.c b/drivers/vdpa/ifc/base/ifcvf.c index 81c68c0..60c7017 100644 --- a/drivers/vdpa/ifc/base/ifcvf.c +++ b/drivers/vdpa/ifc/base/ifcvf.c @@ -202,6 +202,37 @@ IFCVF_WRITE_REG32(val >> 32, hi); } +STATIC void +ifcvf_enable_mq(struct ifcvf_hw *hw) +{ + u8 *mq_cfg; + u8 qid; + int nr_queue = 0; + + for (qid = 0; qid < hw->nr_vring; qid++) { + if (!hw->vring[qid].enable) + continue; + nr_queue++; + } + + if (nr_queue == 0) { + WARNINGOUT("no enabled vring\n"); + return; + } + + mq_cfg = hw->mq_cfg; + if (mq_cfg) { + if (hw->device_type == IFCVF_BLK) { + *(u32 *)mq_cfg = nr_queue; + RTE_LOG(INFO, PMD, "%d queue are enabled\n", nr_queue); + } else { + *(u32 *)mq_cfg = nr_queue / 2; + RTE_LOG(INFO, PMD, "%d queue pairs are enabled\n", + nr_queue / 2); + } + } +} + STATIC int ifcvf_hw_enable(struct ifcvf_hw *hw) { @@ -219,6 +250,7 @@ return -1; } + ifcvf_enable_mq(hw); for (i = 0; i < hw->nr_vring; i++) { IFCVF_WRITE_REG16(i, &cfg->queue_select); io_write64_twopart(hw->vring[i].desc, &cfg->queue_desc_lo, -- 1.8.3.1