From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DC0C2A0581; Wed, 19 Oct 2022 11:32:12 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3988B42905; Wed, 19 Oct 2022 11:31:55 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id 672C14282D for ; Wed, 19 Oct 2022 11:31:53 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666171913; x=1697707913; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=Vw+EQojkuGZtMt5TTcckCCxAzKV7MQu6TroOvfBfjhM=; b=fmrU+tRRRgclgoJICza/bnaHGjIsP4FwANb1Weue9NH8Zl1S9dVnkNl9 f+AWlQffijA38BgaMYifAPanxiNvsTevUbDMiKiU7LsCh8qQPFYQlfcMV bPKKTDTfhGgotmZTYqa3SYlepA0BGbYOsD/teKsKaW68aMLkz9kPln8Cx vSnuVVhyhzKlHijF5JsYF5i3Wf7/nusNZ8sVDWPzkU2/KjQphN8EhOmk6 HZYmX6CgYRRlBu75e7RrV+ShY7qd/V9BsppNljrqTuzNZJ/i89J+YDQOw utKU5oUvXx7JcQnehC3RBRW33vosjpkgk4dzb022pgoTWrGQPeIeQDYN7 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="303976924" X-IronPort-AV: E=Sophos;i="5.95,195,1661842800"; d="scan'208";a="303976924" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2022 02:31:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="771690897" X-IronPort-AV: E=Sophos;i="5.95,195,1661842800"; d="scan'208";a="771690897" Received: from dpdk-dipei.sh.intel.com ([10.67.110.251]) by fmsmga001.fm.intel.com with ESMTP; 19 Oct 2022 02:31:46 -0700 From: Andy Pei To: dev@dpdk.org Cc: chenbo.xia@intel.com, rosen.xu@intel.com, wei.huang@intel.com, gang.cao@intel.com, maxime.coquelin@redhat.com Subject: [PATCH v9 04/12] vdpa/ifc: write queue count to MQ register Date: Wed, 19 Oct 2022 16:41:16 +0800 Message-Id: <1666168884-104665-5-git-send-email-andy.pei@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1666168884-104665-1-git-send-email-andy.pei@intel.com> References: <1661229305-240952-2-git-send-email-andy.pei@intel.com> <1666168884-104665-1-git-send-email-andy.pei@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Write queue count to IFCVF_MQ_OFFSET register to enable multi-queue feature. Signed-off-by: Andy Pei Signed-off-by: Huang Wei Reviewed-by: Chenbo Xia --- drivers/vdpa/ifc/base/ifcvf.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/vdpa/ifc/base/ifcvf.c b/drivers/vdpa/ifc/base/ifcvf.c index 81c68c0..b377126 100644 --- a/drivers/vdpa/ifc/base/ifcvf.c +++ b/drivers/vdpa/ifc/base/ifcvf.c @@ -202,6 +202,37 @@ IFCVF_WRITE_REG32(val >> 32, hi); } +STATIC void +ifcvf_enable_mq(struct ifcvf_hw *hw) +{ + u8 *mq_cfg; + u8 qid; + int nr_queue = 0; + + for (qid = 0; qid < hw->nr_vring; qid++) { + if (!hw->vring[qid].enable) + continue; + nr_queue++; + } + + if (nr_queue == 0) { + WARNINGOUT("no enabled vring\n"); + return; + } + + mq_cfg = hw->mq_cfg; + if (mq_cfg) { + if (hw->device_type == IFCVF_BLK) { + *(u32 *)mq_cfg = nr_queue; + RTE_LOG(INFO, PMD, "%d queues are enabled\n", nr_queue); + } else { + *(u32 *)mq_cfg = nr_queue / 2; + RTE_LOG(INFO, PMD, "%d queue pairs are enabled\n", + nr_queue / 2); + } + } +} + STATIC int ifcvf_hw_enable(struct ifcvf_hw *hw) { @@ -219,6 +250,7 @@ return -1; } + ifcvf_enable_mq(hw); for (i = 0; i < hw->nr_vring; i++) { IFCVF_WRITE_REG16(i, &cfg->queue_select); io_write64_twopart(hw->vring[i].desc, &cfg->queue_desc_lo, -- 1.8.3.1