From: Tyler Retzlaff <roretzla@linux.microsoft.com>
To: dev@dpdk.org
Cc: "Morten Brørup" <mb@smartsharesystems.com>,
"Bruce Richardson" <bruce.richardson@intel.com>,
"Konstantin Ananyev" <konstantin.v.ananyev@yandex.ru>,
"Tyler Retzlaff" <roretzla@linux.microsoft.com>
Subject: [PATCH] eal: fix msvc conditional compile of rte atomic thread fence
Date: Tue, 7 Nov 2023 12:00:16 -0800 [thread overview]
Message-ID: <1699387216-21396-1-git-send-email-roretzla@linux.microsoft.com> (raw)
MSVC does not expose legacy atomics. When the legacy atomics were
excluded rte_atomic_thread_fence was also unintentionally excluded
Adjust the conditional compilation check to expose
rte_atomic_thread_fence.
Fixes: 27da6a123414 ("eal: hide legacy atomics API for MSVC")
Signed-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>
---
lib/eal/x86/include/rte_atomic.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/eal/x86/include/rte_atomic.h b/lib/eal/x86/include/rte_atomic.h
index f754423..74b1b24 100644
--- a/lib/eal/x86/include/rte_atomic.h
+++ b/lib/eal/x86/include/rte_atomic.h
@@ -83,8 +83,6 @@
#define rte_io_rmb() rte_compiler_barrier()
-#ifndef RTE_TOOLCHAIN_MSVC
-
/**
* Synchronization fence between threads based on the specified memory order.
*
@@ -101,6 +99,8 @@
__rte_atomic_thread_fence(memorder);
}
+#ifndef RTE_TOOLCHAIN_MSVC
+
/*------------------------- 16 bit atomic operations -------------------------*/
#ifndef RTE_FORCE_INTRINSICS
--
1.8.3.1
next reply other threads:[~2023-11-07 20:00 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-07 20:00 Tyler Retzlaff [this message]
2023-11-08 8:27 ` Morten Brørup
2023-11-08 13:40 ` Thomas Monjalon
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