From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 96AFA432CA; Tue, 7 Nov 2023 21:00:19 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 859E940698; Tue, 7 Nov 2023 21:00:19 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id 8DDC64025E for ; Tue, 7 Nov 2023 21:00:18 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1086) id DF90120B74C0; Tue, 7 Nov 2023 12:00:17 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com DF90120B74C0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1699387217; bh=2wkgH7eWTjNknu9zUyo6HUrM1Hw0xMu4NY7Mi23x0EI=; h=From:To:Cc:Subject:Date:From; b=nsJk+7mESHj/p5ks96BjWvWPieZheY4QsIfs0eE60Eg7NvgpBxgxTCxiCcqTb6hKr E+XTD6MmvXJz9rU2/tCbOonf0bB+WnwyY1R8PN5BLzBSOJv6DV5fl4ikR6jzTlHF19 2vy6ctCWaEJ9SY1oM8kCKnqswB8rD9CaRzHmXpSg= From: Tyler Retzlaff To: dev@dpdk.org Cc: =?UTF-8?q?Morten=20Br=C3=B8rup?= , Bruce Richardson , Konstantin Ananyev , Tyler Retzlaff Subject: [PATCH] eal: fix msvc conditional compile of rte atomic thread fence Date: Tue, 7 Nov 2023 12:00:16 -0800 Message-Id: <1699387216-21396-1-git-send-email-roretzla@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC does not expose legacy atomics. When the legacy atomics were excluded rte_atomic_thread_fence was also unintentionally excluded Adjust the conditional compilation check to expose rte_atomic_thread_fence. Fixes: 27da6a123414 ("eal: hide legacy atomics API for MSVC") Signed-off-by: Tyler Retzlaff --- lib/eal/x86/include/rte_atomic.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/eal/x86/include/rte_atomic.h b/lib/eal/x86/include/rte_atomic.h index f754423..74b1b24 100644 --- a/lib/eal/x86/include/rte_atomic.h +++ b/lib/eal/x86/include/rte_atomic.h @@ -83,8 +83,6 @@ #define rte_io_rmb() rte_compiler_barrier() -#ifndef RTE_TOOLCHAIN_MSVC - /** * Synchronization fence between threads based on the specified memory order. * @@ -101,6 +99,8 @@ __rte_atomic_thread_fence(memorder); } +#ifndef RTE_TOOLCHAIN_MSVC + /*------------------------- 16 bit atomic operations -------------------------*/ #ifndef RTE_FORCE_INTRINSICS -- 1.8.3.1