From: Anatoly Burakov <anatoly.burakov@intel.com>
To: dev@dpdk.org
Cc: Ian Stokes <ian.stokes@intel.com>,
bruce.richardson@intel.com,
Jacob Keller <jacob.e.keller@intel.com>
Subject: [PATCH v2 061/148] net/ice/base: use "err" instead of "status" in ice_ptp_hw.c
Date: Wed, 12 Jun 2024 16:00:55 +0100 [thread overview]
Message-ID: <16ae540857a71cf93dbd84feed39fecab94ac474.1718204528.git.anatoly.burakov@intel.com> (raw)
In-Reply-To: <cover.1718204528.git.anatoly.burakov@intel.com>
From: Ian Stokes <ian.stokes@intel.com>
With the exception of a few functions, the upstream Linux version of
ice_ptp_hw.c switched to using "int err" early before the initial conversion of
"enum ice_status status" to "int status" was completed. This results in the
upstream version using a different variable name than the out-of-tree shared
file uses. This leads to difference tools like double-blame and patch-detective
reporting differences due to the variable name change.
Standardize the ice_ptp_hw.c file to use "err" instead of "status" across almost
all functions. The exceptions are:
* ice_get_pca9575_handle
* ice_read_sma_ctrl_e810t
* ice_write_sma_ctrl_e810t
* ice_is_pca9575_present
These functions were upstreamed using "int status" and we can leave them alone.
The standard for the rest of this file going forward will be to use "err" going
forward as that matches the style used throughout the rest of the file.
This should have no impact on functionality.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Ian Stokes <ian.stokes@intel.com>
---
drivers/net/ice/base/ice_ptp_hw.c | 2098 ++++++++++++++---------------
1 file changed, 1043 insertions(+), 1055 deletions(-)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c
index 07c8c65050..237c9ffa94 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -115,18 +115,18 @@ static int
ice_read_cgu_reg_e82x(struct ice_hw *hw, u16 addr, u32 *val)
{
struct ice_sbq_msg_input cgu_msg;
- int status;
+ int err;
cgu_msg.opcode = ice_sbq_msg_rd;
cgu_msg.dest_dev = cgu;
cgu_msg.msg_addr_low = addr;
cgu_msg.msg_addr_high = 0x0;
- status = ice_sbq_rw_reg_lp(hw, &cgu_msg, true);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, status %d\n",
- addr, status);
- return status;
+ err = ice_sbq_rw_reg_lp(hw, &cgu_msg, true);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n",
+ addr, err);
+ return err;
}
*val = cgu_msg.data;
@@ -147,7 +147,7 @@ static int
ice_write_cgu_reg_e82x(struct ice_hw *hw, u16 addr, u32 val)
{
struct ice_sbq_msg_input cgu_msg;
- int status;
+ int err;
cgu_msg.opcode = ice_sbq_msg_wr;
cgu_msg.dest_dev = cgu;
@@ -155,11 +155,11 @@ ice_write_cgu_reg_e82x(struct ice_hw *hw, u16 addr, u32 val)
cgu_msg.msg_addr_high = 0x0;
cgu_msg.data = val;
- status = ice_sbq_rw_reg_lp(hw, &cgu_msg, true);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, status %d\n",
- addr, status);
- return status;
+ err = ice_sbq_rw_reg_lp(hw, &cgu_msg, true);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n",
+ addr, err);
+ return err;
}
return 0;
@@ -227,7 +227,7 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,
union nac_cgu_dword22 dw22;
union nac_cgu_dword24 dw24;
union nac_cgu_dword9 dw9;
- int status;
+ int err;
if (clk_freq >= NUM_ICE_TIME_REF_FREQ) {
ice_warn(hw, "Invalid TIME_REF frequency %u\n", clk_freq);
@@ -245,17 +245,17 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,
return ICE_ERR_PARAM;
}
- status = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val);
- if (status)
- return status;
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val);
+ if (err)
+ return err;
- status = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
- if (status)
- return status;
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
+ if (err)
+ return err;
- status = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
- if (status)
- return status;
+ err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
+ if (err)
+ return err;
/* Log the current clock configuration */
ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
@@ -268,67 +268,67 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,
if (dw24.field.ts_pll_enable) {
dw24.field.ts_pll_enable = 0;
- status = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
- if (status)
- return status;
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
+ if (err)
+ return err;
}
/* Set the frequency */
dw9.field.time_ref_freq_sel = clk_freq;
- status = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
- if (status)
- return status;
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
+ if (err)
+ return err;
/* Configure the TS PLL feedback divisor */
- status = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val);
- if (status)
- return status;
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val);
+ if (err)
+ return err;
dw19.field.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div;
dw19.field.tspll_ndivratio = 1;
- status = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val);
- if (status)
- return status;
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val);
+ if (err)
+ return err;
/* Configure the TS PLL post divisor */
- status = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val);
- if (status)
- return status;
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val);
+ if (err)
+ return err;
dw22.field.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div;
dw22.field.time1588clk_sel_div2 = 0;
- status = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val);
- if (status)
- return status;
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val);
+ if (err)
+ return err;
/* Configure the TS PLL pre divisor and clock source */
- status = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
- if (status)
- return status;
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
+ if (err)
+ return err;
dw24.field.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div;
dw24.field.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div;
dw24.field.time_ref_sel = clk_src;
- status = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
- if (status)
- return status;
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
+ if (err)
+ return err;
/* Finally, enable the PLL */
dw24.field.ts_pll_enable = 1;
- status = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
- if (status)
- return status;
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
+ if (err)
+ return err;
/* Wait to verify if the PLL locks */
ice_msec_delay(1, true);
- status = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
- if (status)
- return status;
+ err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
+ if (err)
+ return err;
if (!bwm_lf.field.plllock_true_lock_cri) {
ice_warn(hw, "CGU PLL failed to lock\n");
@@ -364,7 +364,7 @@ ice_cfg_cgu_pll_e825c(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq,
union nac_cgu_dword22 dw22;
union nac_cgu_dword24 dw24;
union nac_cgu_dword9 dw9;
- int status;
+ int err;
if (*clk_freq >= NUM_ICE_TIME_REF_FREQ) {
ice_warn(hw, "Invalid TIME_REF frequency %u\n", *clk_freq);
@@ -382,21 +382,21 @@ ice_cfg_cgu_pll_e825c(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq,
return ICE_ERR_PARAM;
}
- status = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val);
- if (status)
- return status;
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val);
+ if (err)
+ return err;
- status = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
- if (status)
- return status;
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
+ if (err)
+ return err;
- status = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val);
- if (status)
- return status;
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val);
+ if (err)
+ return err;
- status = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
- if (status)
- return status;
+ err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
+ if (err)
+ return err;
/* Log the current clock configuration */
ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
@@ -409,73 +409,73 @@ ice_cfg_cgu_pll_e825c(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq,
if (dw23.field.ts_pll_enable) {
dw23.field.ts_pll_enable = 0;
- status = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C,
- dw23.val);
- if (status)
- return status;
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C,
+ dw23.val);
+ if (err)
+ return err;
}
/* Set the frequency */
dw9.field.time_ref_freq_sel = *clk_freq;
- status = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
- if (status)
- return status;
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
+ if (err)
+ return err;
/* Configure the TS PLL feedback divisor */
- status = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val);
- if (status)
- return status;
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val);
+ if (err)
+ return err;
dw19.field.tspll_fbdiv_intgr = e822_cgu_params[*clk_freq].feedback_div;
dw19.field.tspll_ndivratio = 1;
- status = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val);
- if (status)
- return status;
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val);
+ if (err)
+ return err;
/* Configure the TS PLL post divisor */
- status = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val);
- if (status)
- return status;
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val);
+ if (err)
+ return err;
dw22.field.time1588clk_div = e822_cgu_params[*clk_freq].post_pll_div;
dw22.field.time1588clk_sel_div2 = 0;
- status = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val);
- if (status)
- return status;
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val);
+ if (err)
+ return err;
/* Configure the TS PLL pre divisor and clock source */
- status = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val);
- if (status)
- return status;
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val);
+ if (err)
+ return err;
dw23.field.ref1588_ck_div = e822_cgu_params[*clk_freq].refclk_pre_div;
dw23.field.time_ref_sel = *clk_src;
- status = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val);
- if (status)
- return status;
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val);
+ if (err)
+ return err;
dw24.field.tspll_fbdiv_frac = e822_cgu_params[*clk_freq].frac_n_div;
- status = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
- if (status)
- return status;
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
+ if (err)
+ return err;
/* Finally, enable the PLL */
dw23.field.ts_pll_enable = 1;
- status = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val);
- if (status)
- return status;
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val);
+ if (err)
+ return err;
/* Wait to verify if the PLL locks */
ice_msec_delay(1, true);
- status = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
- if (status)
- return status;
+ err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
+ if (err)
+ return err;
if (!ro_lock.field.plllock_true_lock_cri) {
ice_warn(hw, "CGU PLL failed to lock\n");
@@ -505,19 +505,19 @@ ice_cfg_cgu_pll_e825c(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq,
static int ice_cfg_cgu_pll_dis_sticky_bits_e822(struct ice_hw *hw)
{
union tspll_cntr_bist_settings cntr_bist;
- int status;
+ int err;
- status = ice_read_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS,
- &cntr_bist.val);
- if (status)
- return status;
+ err = ice_read_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS,
+ &cntr_bist.val);
+ if (err)
+ return err;
cntr_bist.field.i_plllock_sel_0 = 0;
cntr_bist.field.i_plllock_sel_1 = 0;
- status = ice_write_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS,
- cntr_bist.val);
- return status;
+ err = ice_write_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS,
+ cntr_bist.val);
+ return err;
}
/**
@@ -530,18 +530,16 @@ static int ice_cfg_cgu_pll_dis_sticky_bits_e822(struct ice_hw *hw)
static int ice_cfg_cgu_pll_dis_sticky_bits_e825c(struct ice_hw *hw)
{
union tspll_bw_tdc_e825c bw_tdc;
- int status;
+ int err;
- status = ice_read_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C,
- &bw_tdc.val);
- if (status)
- return status;
+ err = ice_read_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, &bw_tdc.val);
+ if (err)
+ return err;
bw_tdc.field.i_plllock_sel_1_0 = 0;
- status = ice_write_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C,
- bw_tdc.val);
- return status;
+ err = ice_write_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, bw_tdc.val);
+ return err;
}
/**
@@ -553,11 +551,11 @@ int
ice_cgu_ts_pll_lost_lock_e825c(struct ice_hw *hw, bool *lost_lock)
{
union tspll_ro_lock_e825c ro_lock;
- int status;
+ int err;
- status = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
- if (status)
- return status;
+ err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
+ if (err)
+ return err;
if (ro_lock.field.pllunlock_flag_cri &&
!ro_lock.field.plllock_true_lock_cri)
@@ -575,19 +573,19 @@ ice_cgu_ts_pll_lost_lock_e825c(struct ice_hw *hw, bool *lost_lock)
int ice_cgu_ts_pll_restart_e825c(struct ice_hw *hw)
{
union nac_cgu_dword23_e825c dw23;
- int status;
+ int err;
/* Read the initial values of DW23 */
- status = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val);
- if (status)
- return status;
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val);
+ if (err)
+ return err;
/* Disable the PLL */
dw23.field.ts_pll_enable = 0;
- status = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val);
- if (status)
- return status;
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val);
+ if (err)
+ return err;
/* Wait 5us before reenabling PLL */
ice_usec_delay(5, false);
@@ -595,9 +593,9 @@ int ice_cgu_ts_pll_restart_e825c(struct ice_hw *hw)
/* Re-enable the PLL */
dw23.field.ts_pll_enable = 1;
- status = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val);
- if (status)
- return status;
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val);
+ if (err)
+ return err;
return 0;
}
@@ -624,11 +622,11 @@ int
ice_cgu_bypass_mux_port_active_e825c(struct ice_hw *hw, u8 port, bool *active)
{
union nac_cgu_dword11_e825c dw11;
- int status;
+ int err;
- status = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD11_E825C, &dw11.val);
- if (status)
- return status;
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD11_E825C, &dw11.val);
+ if (err)
+ return err;
if (dw11.field.synce_s_byp_clk == cgu_bypass_mux_port(hw, port))
*active = true;
@@ -651,22 +649,22 @@ ice_cfg_cgu_bypass_mux_e825c(struct ice_hw *hw, u8 port, bool clock_1588,
{
union nac_cgu_dword11_e825c dw11;
union nac_cgu_dword10_e825c dw10;
- int status;
+ int err;
- status = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD11_E825C, &dw11.val);
- if (status)
- return status;
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD11_E825C, &dw11.val);
+ if (err)
+ return err;
- status = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD10_E825C, &dw10.val);
- if (status)
- return status;
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD10_E825C, &dw10.val);
+ if (err)
+ return err;
/* ref_clk_byp1_div */
dw10.field.synce_ethclko_sel = 0x1;
- status = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD10_E825C, dw10.val);
- if (status)
- return status;
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD10_E825C, dw10.val);
+ if (err)
+ return err;
if (!ena)
/* net_ref_clk0 */
@@ -716,24 +714,23 @@ static int ice_get_div_e825c(u16 link_speed, u8 *divider)
int ice_cfg_synce_ethdiv_e825c(struct ice_hw *hw, u8 *divider)
{
union nac_cgu_dword10_e825c dw10;
- int status;
+ int err;
u16 link_speed;
link_speed = hw->port_info->phy.link_info.link_speed;
- status = ice_get_div_e825c(link_speed, divider);
- if (status)
- return status;
+ err = ice_get_div_e825c(link_speed, divider);
+ if (err)
+ return err;
- status = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD10_E825C, &dw10.val);
- if (status)
- return status;
+ err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD10_E825C, &dw10.val);
+ if (err)
+ return err;
/* programmable divider value (from 2 to 16) minus 1 for ETHCLKOUT */
dw10.field.synce_ethdiv_m1 = *divider + 1;
- status = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD10_E825C,
- dw10.val);
- return status;
+ err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD10_E825C, dw10.val);
+ return err;
}
/**
@@ -747,15 +744,15 @@ static int ice_init_cgu_e82x(struct ice_hw *hw)
struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info;
enum ice_time_ref_freq time_ref_freq;
enum ice_clk_src clk_src;
- int status;
+ int err;
/* Disable sticky lock detection so lock status reported is accurate */
if (ice_is_e825c(hw))
- status = ice_cfg_cgu_pll_dis_sticky_bits_e825c(hw);
+ err = ice_cfg_cgu_pll_dis_sticky_bits_e825c(hw);
else
- status = ice_cfg_cgu_pll_dis_sticky_bits_e822(hw);
- if (status)
- return status;
+ err = ice_cfg_cgu_pll_dis_sticky_bits_e822(hw);
+ if (err)
+ return err;
/* Configure the CGU PLL using the parameters from the function
* capabilities.
@@ -763,11 +760,11 @@ static int ice_init_cgu_e82x(struct ice_hw *hw)
time_ref_freq = (enum ice_time_ref_freq)ts_info->time_ref;
clk_src = (enum ice_clk_src)ts_info->clk_src;
if (ice_is_e825c(hw))
- status = ice_cfg_cgu_pll_e825c(hw, &time_ref_freq, &clk_src);
+ err = ice_cfg_cgu_pll_e825c(hw, &time_ref_freq, &clk_src);
else
- status = ice_cfg_cgu_pll_e822(hw, time_ref_freq, clk_src);
- if (status)
- return status;
+ err = ice_cfg_cgu_pll_e822(hw, time_ref_freq, clk_src);
+ if (err)
+ return err;
return 0;
}
@@ -919,7 +916,7 @@ ice_write_phy_eth56g_raw_lp(struct ice_hw *hw, u32 reg_addr, u32 val,
bool lock_sbq)
{
struct ice_sbq_msg_input phy_msg;
- int status;
+ int err;
phy_msg.opcode = ice_sbq_msg_wr;
@@ -929,13 +926,13 @@ ice_write_phy_eth56g_raw_lp(struct ice_hw *hw, u32 reg_addr, u32 val,
phy_msg.data = val;
phy_msg.dest_dev = phy_56g;
- status = ice_sbq_rw_reg_lp(hw, &phy_msg, lock_sbq);
+ err = ice_sbq_rw_reg_lp(hw, &phy_msg, lock_sbq);
- if (status)
+ if (err)
ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n",
- status);
+ err);
- return status;
+ return err;
}
/**
@@ -950,7 +947,7 @@ ice_read_phy_eth56g_raw_lp(struct ice_hw *hw, u32 reg_addr, u32 *val,
bool lock_sbq)
{
struct ice_sbq_msg_input phy_msg;
- int status;
+ int err;
phy_msg.opcode = ice_sbq_msg_rd;
@@ -959,15 +956,15 @@ ice_read_phy_eth56g_raw_lp(struct ice_hw *hw, u32 reg_addr, u32 *val,
phy_msg.dest_dev = phy_56g;
- status = ice_sbq_rw_reg_lp(hw, &phy_msg, lock_sbq);
+ err = ice_sbq_rw_reg_lp(hw, &phy_msg, lock_sbq);
- if (status)
+ if (err)
ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n",
- status);
+ err);
else
*val = phy_msg.data;
- return status;
+ return err;
}
/**
@@ -1028,12 +1025,12 @@ static int
ice_write_phy_reg_eth56g_lp(struct ice_hw *hw, u8 port, u16 offset, u32 val,
bool lock_sbq)
{
- int status;
+ int err;
u32 reg_addr;
- status = ice_phy_port_reg_address_eth56g(port, offset, ®_addr);
- if (status)
- return status;
+ err = ice_phy_port_reg_address_eth56g(port, offset, ®_addr);
+ if (err)
+ return err;
return ice_write_phy_eth56g_raw_lp(hw, reg_addr, val, lock_sbq);
}
@@ -1064,12 +1061,12 @@ static int
ice_read_phy_reg_eth56g_lp(struct ice_hw *hw, u8 port, u16 offset, u32 *val,
bool lock_sbq)
{
- int status;
+ int err;
u32 reg_addr;
- status = ice_phy_port_reg_address_eth56g(port, offset, ®_addr);
- if (status)
- return status;
+ err = ice_phy_port_reg_address_eth56g(port, offset, ®_addr);
+ if (err)
+ return err;
return ice_read_phy_eth56g_raw_lp(hw, reg_addr, val, lock_sbq);
}
@@ -1100,12 +1097,12 @@ static int
ice_phy_port_mem_read_eth56g_lp(struct ice_hw *hw, u8 port, u16 offset,
u32 *val, bool lock_sbq)
{
- int status;
+ int err;
u32 mem_addr;
- status = ice_phy_port_mem_address_eth56g(port, offset, &mem_addr);
- if (status)
- return status;
+ err = ice_phy_port_mem_address_eth56g(port, offset, &mem_addr);
+ if (err)
+ return err;
return ice_read_phy_eth56g_raw_lp(hw, mem_addr, val, lock_sbq);
}
@@ -1137,12 +1134,12 @@ static int
ice_phy_port_mem_write_eth56g_lp(struct ice_hw *hw, u8 port, u16 offset,
u32 val, bool lock_sbq)
{
- int status;
+ int err;
u32 mem_addr;
- status = ice_phy_port_mem_address_eth56g(port, offset, &mem_addr);
- if (status)
- return status;
+ err = ice_phy_port_mem_address_eth56g(port, offset, &mem_addr);
+ if (err)
+ return err;
return ice_write_phy_eth56g_raw_lp(hw, mem_addr, val, lock_sbq);
}
@@ -1217,24 +1214,24 @@ static int
ice_read_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)
{
u16 high_addr = low_addr + sizeof(u32);
- int status;
+ int err;
u32 lo, hi;
if (!ice_is_40b_phy_reg_eth56g(low_addr))
return ICE_ERR_PARAM;
- status = ice_read_phy_reg_eth56g(hw, port, low_addr, &lo);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register %#08x\n, status %d",
- (int)low_addr, status);
- return status;
+ err = ice_read_phy_reg_eth56g(hw, port, low_addr, &lo);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register %#08x\n, err %d",
+ (int)low_addr, err);
+ return err;
}
- status = ice_read_phy_reg_eth56g(hw, port, low_addr + sizeof(u32), &hi);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register %08x\n, status %d",
- high_addr, status);
- return status;
+ err = ice_read_phy_reg_eth56g(hw, port, low_addr + sizeof(u32), &hi);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register %08x\n, err %d",
+ high_addr, err);
+ return err;
}
*val = ((u64)hi << P_REG_40B_HIGH_S) | (lo & P_REG_40B_LOW_M);
@@ -1258,24 +1255,24 @@ static int
ice_read_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)
{
u16 high_addr = low_addr + sizeof(u32);
- int status;
+ int err;
u32 lo, hi;
if (!ice_is_64b_phy_reg_eth56g(low_addr))
return ICE_ERR_PARAM;
- status = ice_read_phy_reg_eth56g(hw, port, low_addr, &lo);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register %#08x\n, status %d",
- low_addr, status);
- return status;
+ err = ice_read_phy_reg_eth56g(hw, port, low_addr, &lo);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register %#08x\n, err %d",
+ low_addr, err);
+ return err;
}
- status = ice_read_phy_reg_eth56g(hw, port, high_addr, &hi);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register %#08x\n, status %d",
- high_addr, status);
- return status;
+ err = ice_read_phy_reg_eth56g(hw, port, high_addr, &hi);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register %#08x\n, err %d",
+ high_addr, err);
+ return err;
}
*val = ((u64)hi << 32) | lo;
@@ -1299,7 +1296,7 @@ static int
ice_write_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
{
u16 high_addr = low_addr + sizeof(u32);
- int status;
+ int err;
u32 lo, hi;
if (!ice_is_40b_phy_reg_eth56g(low_addr))
@@ -1308,18 +1305,18 @@ ice_write_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
lo = (u32)(val & P_REG_40B_LOW_M);
hi = (u32)(val >> P_REG_40B_HIGH_S);
- status = ice_write_phy_reg_eth56g(hw, port, low_addr, lo);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, status %d",
- low_addr, status);
- return status;
+ err = ice_write_phy_reg_eth56g(hw, port, low_addr, lo);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
+ low_addr, err);
+ return err;
}
- status = ice_write_phy_reg_eth56g(hw, port, high_addr, hi);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, status %d",
- high_addr, status);
- return status;
+ err = ice_write_phy_reg_eth56g(hw, port, high_addr, hi);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
+ high_addr, err);
+ return err;
}
return 0;
@@ -1340,7 +1337,7 @@ static int
ice_write_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
{
u16 high_addr = low_addr + sizeof(u32);
- int status;
+ int err;
u32 lo, hi;
if (!ice_is_64b_phy_reg_eth56g(low_addr))
@@ -1349,18 +1346,18 @@ ice_write_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
lo = ICE_LO_DWORD(val);
hi = ICE_HI_DWORD(val);
- status = ice_write_phy_reg_eth56g(hw, port, low_addr, lo);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, status %d",
- low_addr, status);
- return status;
+ err = ice_write_phy_reg_eth56g(hw, port, low_addr, lo);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
+ low_addr, err);
+ return err;
}
- status = ice_write_phy_reg_eth56g(hw, port, high_addr, hi);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, status %d",
- high_addr, status);
- return status;
+ err = ice_write_phy_reg_eth56g(hw, port, high_addr, hi);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
+ high_addr, err);
+ return err;
}
return 0;
@@ -1379,25 +1376,25 @@ ice_write_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
static int
ice_read_phy_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx, u64 *tstamp)
{
- int status;
u16 lo_addr, hi_addr;
u32 lo, hi;
+ int err;
lo_addr = (u16)PHY_TSTAMP_L(idx);
hi_addr = (u16)PHY_TSTAMP_U(idx);
- status = ice_phy_port_mem_read_eth56g(hw, port, lo_addr, &lo);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, status %d\n",
- status);
- return status;
+ err = ice_phy_port_mem_read_eth56g(hw, port, lo_addr, &lo);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n",
+ err);
+ return err;
}
- status = ice_phy_port_mem_read_eth56g(hw, port, hi_addr, &hi);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, status %d\n",
- status);
- return status;
+ err = ice_phy_port_mem_read_eth56g(hw, port, hi_addr, &hi);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n",
+ err);
+ return err;
}
/* For 56G based internal PHYs, the timestamp is reported with the
@@ -1421,16 +1418,16 @@ ice_read_phy_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx, u64 *tstamp)
static int
ice_clear_phy_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx)
{
- int status;
+ int err;
u16 lo_addr;
lo_addr = (u16)PHY_TSTAMP_L(idx);
- status = ice_phy_port_mem_write_eth56g(hw, port, lo_addr, 0);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, status %d\n",
- status);
- return status;
+ err = ice_phy_port_mem_write_eth56g(hw, port, lo_addr, 0);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for port %u, idx %u, err %d\n",
+ port, idx, err);
+ return err;
}
return 0;
@@ -1447,14 +1444,14 @@ ice_clear_phy_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx)
static int
ice_ptp_prep_port_phy_time_eth56g(struct ice_hw *hw, u8 port, u64 phy_time)
{
- int status;
+ int err;
/* Tx case */
- status = ice_write_64b_phy_reg_eth56g(hw, port,
+ err = ice_write_64b_phy_reg_eth56g(hw, port,
PHY_REG_TX_TIMER_INC_PRE_L,
phy_time);
- if (status)
- return status;
+ if (err)
+ return err;
/* Rx case */
return ice_write_64b_phy_reg_eth56g(hw, port,
@@ -1475,7 +1472,6 @@ ice_ptp_prep_port_phy_time_eth56g(struct ice_hw *hw, u8 port, u64 phy_time)
static int
ice_ptp_prep_phy_time_eth56g(struct ice_hw *hw, u32 time)
{
- int status;
u64 phy_time;
u8 port;
@@ -1485,15 +1481,15 @@ ice_ptp_prep_phy_time_eth56g(struct ice_hw *hw, u32 time)
phy_time = (u64)time << 32;
for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
+ int err;
if (!(hw->ena_lports & BIT(port)))
continue;
- status = ice_ptp_prep_port_phy_time_eth56g(hw, port,
- phy_time);
+ err = ice_ptp_prep_port_phy_time_eth56g(hw, port, phy_time);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, status %d\n",
- port, status);
- return status;
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n",
+ port, err);
+ return err;
}
}
@@ -1521,44 +1517,40 @@ int
ice_ptp_prep_port_adj_eth56g(struct ice_hw *hw, u8 port, s64 time,
bool lock_sbq)
{
- int status;
u32 l_time, u_time;
+ int err;
l_time = ICE_LO_DWORD(time);
u_time = ICE_HI_DWORD(time);
/* Tx case */
- status = ice_write_phy_reg_eth56g_lp(hw, port,
- PHY_REG_TX_TIMER_INC_PRE_L,
- l_time, lock_sbq);
- if (status)
+ err = ice_write_phy_reg_eth56g_lp(hw, port, PHY_REG_TX_TIMER_INC_PRE_L,
+ l_time, lock_sbq);
+ if (err)
goto exit_err;
- status = ice_write_phy_reg_eth56g_lp(hw, port,
- PHY_REG_TX_TIMER_INC_PRE_U,
- u_time, lock_sbq);
- if (status)
+ err = ice_write_phy_reg_eth56g_lp(hw, port, PHY_REG_TX_TIMER_INC_PRE_U,
+ u_time, lock_sbq);
+ if (err)
goto exit_err;
/* Rx case */
- status = ice_write_phy_reg_eth56g_lp(hw, port,
- PHY_REG_RX_TIMER_INC_PRE_L,
- l_time, lock_sbq);
- if (status)
+ err = ice_write_phy_reg_eth56g_lp(hw, port, PHY_REG_RX_TIMER_INC_PRE_L,
+ l_time, lock_sbq);
+ if (err)
goto exit_err;
- status = ice_write_phy_reg_eth56g_lp(hw, port,
- PHY_REG_RX_TIMER_INC_PRE_U,
- u_time, lock_sbq);
- if (status)
+ err = ice_write_phy_reg_eth56g_lp(hw, port, PHY_REG_RX_TIMER_INC_PRE_U,
+ u_time, lock_sbq);
+ if (err)
goto exit_err;
return 0;
exit_err:
- ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, status %d\n",
- port, status);
- return status;
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n",
+ port, err);
+ return err;
}
/**
@@ -1575,7 +1567,7 @@ ice_ptp_prep_port_adj_eth56g(struct ice_hw *hw, u8 port, s64 time,
static int
ice_ptp_prep_phy_adj_eth56g(struct ice_hw *hw, s32 adj, bool lock_sbq)
{
- int status = 0;
+ int err = 0;
s64 cycles;
u8 port;
@@ -1589,13 +1581,12 @@ ice_ptp_prep_phy_adj_eth56g(struct ice_hw *hw, s32 adj, bool lock_sbq)
if (!(hw->ena_lports & BIT(port)))
continue;
- status = ice_ptp_prep_port_adj_eth56g(hw, port, cycles,
- lock_sbq);
- if (status)
+ err = ice_ptp_prep_port_adj_eth56g(hw, port, cycles, lock_sbq);
+ if (err)
break;
}
- return status;
+ return err;
}
/**
@@ -1610,19 +1601,18 @@ ice_ptp_prep_phy_adj_eth56g(struct ice_hw *hw, s32 adj, bool lock_sbq)
static int
ice_ptp_prep_phy_incval_eth56g(struct ice_hw *hw, u64 incval)
{
- int status;
u8 port;
for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
+ int err;
if (!(hw->ena_lports & BIT(port)))
continue;
- status = ice_write_40b_phy_reg_eth56g(hw, port,
- PHY_REG_TIMETUS_L,
- incval);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, status %d\n",
- port, status);
- return status;
+ err = ice_write_40b_phy_reg_eth56g(hw, port, PHY_REG_TIMETUS_L,
+ incval);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n",
+ port, err);
+ return err;
}
}
@@ -1640,14 +1630,14 @@ ice_ptp_prep_phy_incval_eth56g(struct ice_hw *hw, u64 incval)
int
ice_ptp_read_phy_incval_eth56g(struct ice_hw *hw, u8 port, u64 *incval)
{
- int status;
+ int err;
- status = ice_read_40b_phy_reg_eth56g(hw, port, PHY_REG_TIMETUS_L,
+ err = ice_read_40b_phy_reg_eth56g(hw, port, PHY_REG_TIMETUS_L,
incval);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read TIMETUS_L, status %d\n",
- status);
- return status;
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read TIMETUS_L, err %d\n",
+ err);
+ return err;
}
ice_debug(hw, ICE_DBG_PTP, "read INCVAL = 0x%016llx\n",
@@ -1672,7 +1662,7 @@ ice_ptp_read_phy_incval_eth56g(struct ice_hw *hw, u8 port, u64 *incval)
static int
ice_ptp_prep_phy_adj_target_eth56g(struct ice_hw *hw, u32 target_time)
{
- int status;
+ int err;
u8 port;
for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
@@ -1681,40 +1671,40 @@ ice_ptp_prep_phy_adj_target_eth56g(struct ice_hw *hw, u32 target_time)
/* Tx case */
/* No sub-nanoseconds data */
- status = ice_write_phy_reg_eth56g_lp(hw, port,
- PHY_REG_TX_TIMER_CNT_ADJ_L,
- 0, true);
- if (status)
+ err = ice_write_phy_reg_eth56g_lp(hw, port,
+ PHY_REG_TX_TIMER_CNT_ADJ_L,
+ 0, true);
+ if (err)
goto exit_err;
- status = ice_write_phy_reg_eth56g_lp(hw, port,
- PHY_REG_TX_TIMER_CNT_ADJ_U,
- target_time, true);
- if (status)
+ err = ice_write_phy_reg_eth56g_lp(hw, port,
+ PHY_REG_TX_TIMER_CNT_ADJ_U,
+ target_time, true);
+ if (err)
goto exit_err;
/* Rx case */
/* No sub-nanoseconds data */
- status = ice_write_phy_reg_eth56g_lp(hw, port,
- PHY_REG_RX_TIMER_CNT_ADJ_L,
- 0, true);
- if (status)
+ err = ice_write_phy_reg_eth56g_lp(hw, port,
+ PHY_REG_RX_TIMER_CNT_ADJ_L,
+ 0, true);
+ if (err)
goto exit_err;
- status = ice_write_phy_reg_eth56g_lp(hw, port,
- PHY_REG_RX_TIMER_CNT_ADJ_U,
- target_time, true);
- if (status)
+ err = ice_write_phy_reg_eth56g_lp(hw, port,
+ PHY_REG_RX_TIMER_CNT_ADJ_U,
+ target_time, true);
+ if (err)
goto exit_err;
}
return 0;
exit_err:
- ice_debug(hw, ICE_DBG_PTP, "Failed to write target time for port %u, status %d\n",
- port, status);
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write target time for port %u, err %d\n",
+ port, err);
- return status;
+ return err;
}
/**
@@ -1730,27 +1720,27 @@ int
ice_ptp_read_port_capture_eth56g(struct ice_hw *hw, u8 port, u64 *tx_ts,
u64 *rx_ts)
{
- int status;
+ int err;
/* Tx case */
- status = ice_read_64b_phy_reg_eth56g(hw, port, PHY_REG_TX_CAPTURE_L,
- tx_ts);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, status %d\n",
- status);
- return status;
+ err = ice_read_64b_phy_reg_eth56g(hw, port, PHY_REG_TX_CAPTURE_L,
+ tx_ts);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n",
+ err);
+ return err;
}
ice_debug(hw, ICE_DBG_PTP, "tx_init = %#016llx\n",
(unsigned long long)*tx_ts);
/* Rx case */
- status = ice_read_64b_phy_reg_eth56g(hw, port, PHY_REG_RX_CAPTURE_L,
- rx_ts);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, status %d\n",
- status);
- return status;
+ err = ice_read_64b_phy_reg_eth56g(hw, port, PHY_REG_RX_CAPTURE_L,
+ rx_ts);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n",
+ err);
+ return err;
}
ice_debug(hw, ICE_DBG_PTP, "rx_init = %#016llx\n",
@@ -1772,7 +1762,7 @@ int
ice_ptp_one_port_cmd_eth56g(struct ice_hw *hw, u8 port,
enum ice_ptp_tmr_cmd cmd, bool lock_sbq)
{
- int status;
+ int err;
u32 cmd_val, val;
u8 tmr_idx;
@@ -1801,46 +1791,46 @@ ice_ptp_one_port_cmd_eth56g(struct ice_hw *hw, u8 port,
/* Tx case */
/* Read, modify, write */
- status = ice_read_phy_reg_eth56g_lp(hw, port, PHY_REG_TX_TMR_CMD, &val,
+ err = ice_read_phy_reg_eth56g_lp(hw, port, PHY_REG_TX_TMR_CMD, &val,
lock_sbq);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_TMR_CMD, status %d\n",
- status);
- return status;
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_TMR_CMD, err %d\n",
+ err);
+ return err;
}
/* Modify necessary bits only and perform write */
val &= ~TS_CMD_MASK;
val |= cmd_val;
- status = ice_write_phy_reg_eth56g_lp(hw, port, PHY_REG_TX_TMR_CMD, val,
+ err = ice_write_phy_reg_eth56g_lp(hw, port, PHY_REG_TX_TMR_CMD, val,
lock_sbq);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, status %d\n",
- status);
- return status;
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n",
+ err);
+ return err;
}
/* Rx case */
/* Read, modify, write */
- status = ice_read_phy_reg_eth56g_lp(hw, port, PHY_REG_RX_TMR_CMD, &val,
+ err = ice_read_phy_reg_eth56g_lp(hw, port, PHY_REG_RX_TMR_CMD, &val,
lock_sbq);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_TMR_CMD, status %d\n",
- status);
- return status;
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_TMR_CMD, err %d\n",
+ err);
+ return err;
}
/* Modify necessary bits only and perform write */
val &= ~TS_CMD_MASK;
val |= cmd_val;
- status = ice_write_phy_reg_eth56g_lp(hw, port, PHY_REG_RX_TMR_CMD, val,
+ err = ice_write_phy_reg_eth56g_lp(hw, port, PHY_REG_RX_TMR_CMD, val,
lock_sbq);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, status %d\n",
- status);
- return status;
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n",
+ err);
+ return err;
}
return 0;
@@ -1859,16 +1849,16 @@ int
ice_ptp_port_cmd_eth56g(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
bool lock_sbq)
{
- int status;
+ int err;
u8 port;
for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
if (!(hw->ena_lports & BIT(port)))
continue;
- status = ice_ptp_one_port_cmd_eth56g(hw, port, cmd, lock_sbq);
- if (status)
- return status;
+ err = ice_ptp_one_port_cmd_eth56g(hw, port, cmd, lock_sbq);
+ if (err)
+ return err;
}
return 0;
@@ -1905,8 +1895,8 @@ ice_calc_fixed_tx_offset_eth56g(struct ice_hw *hw,
int ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port)
{
enum ice_ptp_link_spd link_spd = ICE_PTP_LNK_SPD_10G;
- int status;
u64 total_offset;
+ int err;
total_offset = ice_calc_fixed_tx_offset_eth56g(hw, link_spd);
@@ -1914,11 +1904,10 @@ int ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port)
* PHY and indicate that the Tx offset is ready. After this,
* timestamps will be enabled.
*/
- status = ice_write_64b_phy_reg_eth56g(hw, port,
- PHY_REG_TOTAL_TX_OFFSET_L,
- total_offset);
- if (status)
- return status;
+ err = ice_write_64b_phy_reg_eth56g(hw, port, PHY_REG_TOTAL_TX_OFFSET_L,
+ total_offset);
+ if (err)
+ return err;
return ice_write_phy_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 1);
}
@@ -1959,7 +1948,7 @@ ice_calc_fixed_rx_offset_eth56g(struct ice_hw *hw,
*/
int ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port)
{
- int status;
+ int err;
u64 total_offset;
total_offset = ice_calc_fixed_rx_offset_eth56g(hw, 0);
@@ -1968,11 +1957,10 @@ int ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port)
* PHY and indicate that the Rx offset is ready. After this,
* timestamps will be enabled.
*/
- status = ice_write_64b_phy_reg_eth56g(hw, port,
- PHY_REG_TOTAL_RX_OFFSET_L,
- total_offset);
- if (status)
- return status;
+ err = ice_write_64b_phy_reg_eth56g(hw, port, PHY_REG_TOTAL_RX_OFFSET_L,
+ total_offset);
+ if (err)
+ return err;
return ice_write_phy_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 1);
}
@@ -1991,10 +1979,10 @@ static int
ice_read_phy_and_phc_time_eth56g(struct ice_hw *hw, u8 port, u64 *phy_time,
u64 *phc_time)
{
- int status;
u64 tx_time, rx_time;
u32 zo, lo;
u8 tmr_idx;
+ int err;
tmr_idx = ice_get_ptp_src_clock_index(hw);
@@ -2002,9 +1990,9 @@ ice_read_phy_and_phc_time_eth56g(struct ice_hw *hw, u8 port, u64 *phy_time,
ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME);
/* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */
- status = ice_ptp_one_port_cmd_eth56g(hw, port, ICE_PTP_READ_TIME, true);
- if (status)
- return status;
+ err = ice_ptp_one_port_cmd_eth56g(hw, port, ICE_PTP_READ_TIME, true);
+ if (err)
+ return err;
/* Issue the sync to start the ICE_PTP_READ_TIME capture */
ice_ptp_exec_tmr_cmd(hw);
@@ -2015,9 +2003,9 @@ ice_read_phy_and_phc_time_eth56g(struct ice_hw *hw, u8 port, u64 *phy_time,
*phc_time = (u64)lo << 32 | zo;
/* Read the captured PHY time from the PHY shadow registers */
- status = ice_ptp_read_port_capture_eth56g(hw, port, &tx_time, &rx_time);
- if (status)
- return status;
+ err = ice_ptp_read_port_capture_eth56g(hw, port, &tx_time, &rx_time);
+ if (err)
+ return err;
/* If the PHY Tx and Rx timers don't match, log a warning message.
* Note that this should not happen in normal circumstances since the
@@ -2048,16 +2036,16 @@ ice_read_phy_and_phc_time_eth56g(struct ice_hw *hw, u8 port, u64 *phy_time,
static int ice_sync_phy_timer_eth56g(struct ice_hw *hw, u8 port)
{
u64 phc_time, phy_time, difference;
- int status;
+ int err;
if (!ice_ptp_lock(hw)) {
ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n");
return ICE_ERR_NOT_READY;
}
- status = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time,
- &phc_time);
- if (status)
+ err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time,
+ &phc_time);
+ if (err)
goto err_unlock;
/* Calculate the amount required to add to the port time in order for
@@ -2072,12 +2060,12 @@ static int ice_sync_phy_timer_eth56g(struct ice_hw *hw, u8 port)
ice_ptp_src_cmd(hw, ICE_PTP_NOP);
difference = phc_time - phy_time;
- status = ice_ptp_prep_port_adj_eth56g(hw, port, (s64)difference, true);
- if (status)
+ err = ice_ptp_prep_port_adj_eth56g(hw, port, (s64)difference, true);
+ if (err)
goto err_unlock;
- status = ice_ptp_one_port_cmd_eth56g(hw, port, ICE_PTP_ADJ_TIME, true);
- if (status)
+ err = ice_ptp_one_port_cmd_eth56g(hw, port, ICE_PTP_ADJ_TIME, true);
+ if (err)
goto err_unlock;
/* Issue the sync to activate the time adjustment */
@@ -2087,9 +2075,9 @@ static int ice_sync_phy_timer_eth56g(struct ice_hw *hw, u8 port)
* verify that the time was properly adjusted.
*/
- status = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time,
- &phc_time);
- if (status)
+ err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time,
+ &phc_time);
+ if (err)
goto err_unlock;
ice_info(hw, "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n",
@@ -2098,7 +2086,7 @@ static int ice_sync_phy_timer_eth56g(struct ice_hw *hw, u8 port)
err_unlock:
ice_ptp_unlock(hw);
- return status;
+ return err;
}
/**
@@ -2114,15 +2102,15 @@ static int ice_sync_phy_timer_eth56g(struct ice_hw *hw, u8 port)
int
ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset)
{
- int status;
+ int err;
- status = ice_write_phy_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 0);
- if (status)
- return status;
+ err = ice_write_phy_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 0);
+ if (err)
+ return err;
- status = ice_write_phy_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 0);
- if (status)
- return status;
+ err = ice_write_phy_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 0);
+ if (err)
+ return err;
ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port);
@@ -2143,16 +2131,16 @@ ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset)
int
ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool bypass)
{
- int status;
+ int err;
u32 lo, hi;
u64 incval;
u8 tmr_idx;
tmr_idx = ice_get_ptp_src_clock_index(hw);
- status = ice_stop_phy_timer_eth56g(hw, port, false);
- if (status)
- return status;
+ err = ice_stop_phy_timer_eth56g(hw, port, false);
+ if (err)
+ return err;
ice_ptp_src_cmd(hw, ICE_PTP_NOP);
@@ -2160,31 +2148,31 @@ ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool bypass)
hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));
incval = (u64)hi << 32 | lo;
- status = ice_write_40b_phy_reg_eth56g(hw, port, PHY_REG_TIMETUS_L,
- incval);
- if (status)
- return status;
+ err = ice_write_40b_phy_reg_eth56g(hw, port, PHY_REG_TIMETUS_L,
+ incval);
+ if (err)
+ return err;
- status = ice_ptp_one_port_cmd_eth56g(hw, port, ICE_PTP_INIT_INCVAL,
+ err = ice_ptp_one_port_cmd_eth56g(hw, port, ICE_PTP_INIT_INCVAL,
true);
- if (status)
- return status;
+ if (err)
+ return err;
ice_ptp_exec_tmr_cmd(hw);
- status = ice_sync_phy_timer_eth56g(hw, port);
- if (status)
- return status;
+ err = ice_sync_phy_timer_eth56g(hw, port);
+ if (err)
+ return err;
/* Program the Tx offset */
- status = ice_phy_cfg_tx_offset_eth56g(hw, port);
- if (status)
- return status;
+ err = ice_phy_cfg_tx_offset_eth56g(hw, port);
+ if (err)
+ return err;
/* Program the Rx offset */
- status = ice_phy_cfg_rx_offset_eth56g(hw, port);
- if (status)
- return status;
+ err = ice_phy_cfg_rx_offset_eth56g(hw, port);
+ if (err)
+ return err;
ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port);
@@ -2199,7 +2187,7 @@ ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool bypass)
*/
static int ice_ptp_init_phc_eth56g(struct ice_hw *hw)
{
- int status = 0;
+ int err = 0;
u32 regval;
/* Enable reading switch and PHY registers over the sideband queue */
@@ -2211,46 +2199,46 @@ static int ice_ptp_init_phc_eth56g(struct ice_hw *hw)
wr32(hw, PF_SB_REM_DEV_CTL, regval);
/* Initialize the Clock Generation Unit */
- status = ice_init_cgu_e82x(hw);
+ err = ice_init_cgu_e82x(hw);
- return status;
+ return err;
}
/**
* ice_ptp_read_tx_hwtstamp_status_eth56g - Get the current TX timestamp
- * status mask. Returns the mask of ports where TX timestamps are available
+ * err mask. Returns the mask of ports where TX timestamps are available
* @hw: pointer to the HW struct
- * @ts_status: the timestamp mask pointer
+ * @ts_err: the timestamp mask pointer
*/
int
-ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status)
+ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_err)
{
- int status;
+ int err;
- status = ice_read_phy_eth56g_raw_lp(hw, PHY_PTP_INT_STATUS, ts_status,
+ err = ice_read_phy_eth56g_raw_lp(hw, PHY_PTP_INT_STATUS, ts_err,
true);
- if (status)
- return status;
+ if (err)
+ return err;
- ice_debug(hw, ICE_DBG_PTP, "PHY interrupt status: %x\n", *ts_status);
+ ice_debug(hw, ICE_DBG_PTP, "PHY interrupt err: %x\n", *ts_err);
return 0;
}
/**
- * ice_ptp_init_phy_cfg - Get the current TX timestamp status
+ * ice_ptp_init_phy_cfg - Get the current TX timestamp err
* mask. Returns the mask of ports where TX timestamps are available
* @hw: pointer to the HW struct
*/
int ice_ptp_init_phy_cfg(struct ice_hw *hw)
{
- int status;
+ int err;
u32 phy_rev;
- status = ice_read_phy_eth56g_raw_lp(hw, PHY_REG_REVISION, &phy_rev,
+ err = ice_read_phy_eth56g_raw_lp(hw, PHY_REG_REVISION, &phy_rev,
true);
- if (status)
- return status;
+ if (err)
+ return err;
if (phy_rev == PHY_REVISION_ETH56G) {
hw->phy_cfg = ICE_PHY_ETH56G;
@@ -2416,16 +2404,16 @@ ice_read_phy_reg_e822_lp(struct ice_hw *hw, u8 port, u16 offset, u32 *val,
bool lock_sbq)
{
struct ice_sbq_msg_input msg = {0};
- int status;
+ int err;
ice_fill_phy_msg_e822(&msg, port, offset);
msg.opcode = ice_sbq_msg_rd;
- status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n",
- status);
- return status;
+ err = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
+ err);
+ return err;
}
*val = msg.data;
@@ -2454,9 +2442,9 @@ ice_read_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 *val)
static int
ice_read_40b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)
{
- int status;
u32 low, high;
u16 high_addr;
+ int err;
/* Only operate on registers known to be split into two 32bit
* registers.
@@ -2467,18 +2455,18 @@ ice_read_40b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)
return ICE_ERR_PARAM;
}
- status = ice_read_phy_reg_e822(hw, port, low_addr, &low);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, status %d",
- low_addr, status);
- return status;
+ err = ice_read_phy_reg_e822(hw, port, low_addr, &low);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, err %d",
+ low_addr, err);
+ return err;
}
- status = ice_read_phy_reg_e822(hw, port, high_addr, &high);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, status %d",
- high_addr, status);
- return status;
+ err = ice_read_phy_reg_e822(hw, port, high_addr, &high);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, err %d",
+ high_addr, err);
+ return err;
}
*val = (u64)high << P_REG_40B_HIGH_S | (low & P_REG_40B_LOW_M);
@@ -2501,9 +2489,9 @@ ice_read_40b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)
static int
ice_read_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)
{
- int status;
u32 low, high;
u16 high_addr;
+ int err;
/* Only operate on registers known to be split into two 32bit
* registers.
@@ -2514,18 +2502,18 @@ ice_read_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)
return ICE_ERR_PARAM;
}
- status = ice_read_phy_reg_e822(hw, port, low_addr, &low);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, status %d",
- low_addr, status);
- return status;
+ err = ice_read_phy_reg_e822(hw, port, low_addr, &low);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, err %d",
+ low_addr, err);
+ return err;
}
- status = ice_read_phy_reg_e822(hw, port, high_addr, &high);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, status %d",
- high_addr, status);
- return status;
+ err = ice_read_phy_reg_e822(hw, port, high_addr, &high);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, err %d",
+ high_addr, err);
+ return err;
}
*val = (u64)high << 32 | low;
@@ -2548,17 +2536,17 @@ ice_write_phy_reg_e822_lp(struct ice_hw *hw, u8 port, u16 offset, u32 val,
bool lock_sbq)
{
struct ice_sbq_msg_input msg = {0};
- int status;
+ int err;
ice_fill_phy_msg_e822(&msg, port, offset);
msg.opcode = ice_sbq_msg_wr;
msg.data = val;
- status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n",
- status);
- return status;
+ err = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
+ err);
+ return err;
}
return 0;
@@ -2583,9 +2571,9 @@ ice_write_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 val)
static int
ice_write_40b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
{
- int status;
u32 low, high;
u16 high_addr;
+ int err;
/* Only operate on registers known to be split into a lower 8 bit
* register and an upper 32 bit register.
@@ -2599,18 +2587,18 @@ ice_write_40b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
low = (u32)(val & P_REG_40B_LOW_M);
high = (u32)(val >> P_REG_40B_HIGH_S);
- status = ice_write_phy_reg_e822(hw, port, low_addr, low);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, status %d",
- low_addr, status);
- return status;
+ err = ice_write_phy_reg_e822(hw, port, low_addr, low);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
+ low_addr, err);
+ return err;
}
- status = ice_write_phy_reg_e822(hw, port, high_addr, high);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, status %d",
- high_addr, status);
- return status;
+ err = ice_write_phy_reg_e822(hw, port, high_addr, high);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
+ high_addr, err);
+ return err;
}
return 0;
@@ -2631,9 +2619,9 @@ ice_write_40b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
static int
ice_write_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
{
- int status;
u32 low, high;
u16 high_addr;
+ int err;
/* Only operate on registers known to be split into two 32bit
* registers.
@@ -2647,18 +2635,18 @@ ice_write_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
low = ICE_LO_DWORD(val);
high = ICE_HI_DWORD(val);
- status = ice_write_phy_reg_e822(hw, port, low_addr, low);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, status %d",
- low_addr, status);
- return status;
+ err = ice_write_phy_reg_e822(hw, port, low_addr, low);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
+ low_addr, err);
+ return err;
}
- status = ice_write_phy_reg_e822(hw, port, high_addr, high);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, status %d",
- high_addr, status);
- return status;
+ err = ice_write_phy_reg_e822(hw, port, high_addr, high);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
+ high_addr, err);
+ return err;
}
return 0;
@@ -2710,23 +2698,24 @@ ice_read_quad_reg_e822_lp(struct ice_hw *hw, u8 quad, u16 offset, u32 *val,
bool lock_sbq)
{
struct ice_sbq_msg_input msg = {0};
- int status;
+ int err;
- status = ice_fill_quad_msg_e822(&msg, quad, offset);
- if (status)
- goto exit_err;
+ err = ice_fill_quad_msg_e822(&msg, quad, offset);
+ if (err)
+ return err;
msg.opcode = ice_sbq_msg_rd;
- status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
-exit_err:
- if (status)
- ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n",
- status);
- else
- *val = msg.data;
+ err = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
+ err);
+ return err;
+ }
- return ICE_SUCCESS;
+ *val = msg.data;
+
+ return 0;
}
int
@@ -2751,22 +2740,23 @@ ice_write_quad_reg_e822_lp(struct ice_hw *hw, u8 quad, u16 offset, u32 val,
bool lock_sbq)
{
struct ice_sbq_msg_input msg = {0};
- int status;
+ int err;
- status = ice_fill_quad_msg_e822(&msg, quad, offset);
- if (status)
- goto exit_err;
+ err = ice_fill_quad_msg_e822(&msg, quad, offset);
+ if (err)
+ return err;
msg.opcode = ice_sbq_msg_wr;
msg.data = val;
- status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
-exit_err:
- if (status)
- ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n",
- status);
+ err = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
+ err);
+ return err;
+ }
- return ICE_SUCCESS;
+ return 0;
}
int
@@ -2789,25 +2779,25 @@ ice_write_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 val)
static int
ice_read_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp)
{
- int status;
u16 lo_addr, hi_addr;
u32 lo, hi;
+ int err;
lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx);
hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx);
- status = ice_read_quad_reg_e822(hw, quad, lo_addr, &lo);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, status %d\n",
- status);
- return status;
+ err = ice_read_quad_reg_e822(hw, quad, lo_addr, &lo);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n",
+ err);
+ return err;
}
- status = ice_read_quad_reg_e822(hw, quad, hi_addr, &hi);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, status %d\n",
- status);
- return status;
+ err = ice_read_quad_reg_e822(hw, quad, hi_addr, &hi);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n",
+ err);
+ return err;
}
/* For E822 based internal PHYs, the timestamp is reported with the
@@ -2844,24 +2834,24 @@ ice_read_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp)
static int
ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx)
{
- int status;
+ int err;
u16 lo_addr, hi_addr;
lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx);
hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx);
- status = ice_write_quad_reg_e822(hw, quad, lo_addr, 0);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, status %d\n",
- status);
- return status;
+ err = ice_write_quad_reg_e822(hw, quad, lo_addr, 0);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, err %d\n",
+ err);
+ return err;
}
- status = ice_write_quad_reg_e822(hw, quad, hi_addr, 0);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, status %d\n",
- status);
- return status;
+ err = ice_write_quad_reg_e822(hw, quad, hi_addr, 0);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, err %d\n",
+ err);
+ return err;
}
return 0;
@@ -2878,14 +2868,14 @@ int ice_ptp_set_vernier_wl(struct ice_hw *hw)
u8 port;
for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
- int status;
+ int err;
- status = ice_write_phy_reg_e822_lp(hw, port, P_REG_WL,
- PTP_VERNIER_WL, true);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, status %d\n",
- port, status);
- return status;
+ err = ice_write_phy_reg_e822_lp(hw, port, P_REG_WL,
+ PTP_VERNIER_WL, true);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, err %d\n",
+ port, err);
+ return err;
}
}
@@ -2900,7 +2890,7 @@ int ice_ptp_set_vernier_wl(struct ice_hw *hw)
*/
static int ice_ptp_init_phc_e822(struct ice_hw *hw)
{
- int status;
+ int err;
u32 regval;
/* Enable reading switch and PHY registers over the sideband queue */
@@ -2912,9 +2902,9 @@ static int ice_ptp_init_phc_e822(struct ice_hw *hw)
wr32(hw, PF_SB_REM_DEV_CTL, regval);
/* Initialize the Clock Generation Unit */
- status = ice_init_cgu_e82x(hw);
- if (status)
- return status;
+ err = ice_init_cgu_e82x(hw);
+ if (err)
+ return err;
/* Set window length for all the ports */
return ice_ptp_set_vernier_wl(hw);
@@ -2933,8 +2923,8 @@ static int ice_ptp_init_phc_e822(struct ice_hw *hw)
static int
ice_ptp_prep_phy_time_e822(struct ice_hw *hw, u32 time)
{
- int status;
u64 phy_time;
+ int err;
u8 port;
/* The time represents the upper 32 bits of the PHY timer, so we need
@@ -2945,27 +2935,27 @@ ice_ptp_prep_phy_time_e822(struct ice_hw *hw, u32 time)
for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
/* Tx case */
- status = ice_write_64b_phy_reg_e822(hw, port,
- P_REG_TX_TIMER_INC_PRE_L,
- phy_time);
- if (status)
+ err = ice_write_64b_phy_reg_e822(hw, port,
+ P_REG_TX_TIMER_INC_PRE_L,
+ phy_time);
+ if (err)
goto exit_err;
/* Rx case */
- status = ice_write_64b_phy_reg_e822(hw, port,
- P_REG_RX_TIMER_INC_PRE_L,
- phy_time);
- if (status)
+ err = ice_write_64b_phy_reg_e822(hw, port,
+ P_REG_RX_TIMER_INC_PRE_L,
+ phy_time);
+ if (err)
goto exit_err;
}
return 0;
exit_err:
- ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, status %d\n",
- port, status);
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n",
+ port, err);
- return status;
+ return err;
}
/**
@@ -2989,40 +2979,40 @@ int
ice_ptp_prep_port_adj_e822(struct ice_hw *hw, u8 port, s64 time,
bool lock_sbq)
{
- int status;
u32 l_time, u_time;
+ int err;
l_time = ICE_LO_DWORD(time);
u_time = ICE_HI_DWORD(time);
/* Tx case */
- status = ice_write_phy_reg_e822_lp(hw, port, P_REG_TX_TIMER_INC_PRE_L,
- l_time, lock_sbq);
- if (status)
+ err = ice_write_phy_reg_e822_lp(hw, port, P_REG_TX_TIMER_INC_PRE_L,
+ l_time, lock_sbq);
+ if (err)
goto exit_err;
- status = ice_write_phy_reg_e822_lp(hw, port, P_REG_TX_TIMER_INC_PRE_U,
- u_time, lock_sbq);
- if (status)
+ err = ice_write_phy_reg_e822_lp(hw, port, P_REG_TX_TIMER_INC_PRE_U,
+ u_time, lock_sbq);
+ if (err)
goto exit_err;
/* Rx case */
- status = ice_write_phy_reg_e822_lp(hw, port, P_REG_RX_TIMER_INC_PRE_L,
- l_time, lock_sbq);
- if (status)
+ err = ice_write_phy_reg_e822_lp(hw, port, P_REG_RX_TIMER_INC_PRE_L,
+ l_time, lock_sbq);
+ if (err)
goto exit_err;
- status = ice_write_phy_reg_e822_lp(hw, port, P_REG_RX_TIMER_INC_PRE_U,
- u_time, lock_sbq);
- if (status)
+ err = ice_write_phy_reg_e822_lp(hw, port, P_REG_RX_TIMER_INC_PRE_U,
+ u_time, lock_sbq);
+ if (err)
goto exit_err;
return 0;
exit_err:
- ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, status %d\n",
- port, status);
- return status;
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n",
+ port, err);
+ return err;
}
/**
@@ -3052,12 +3042,11 @@ ice_ptp_prep_phy_adj_e822(struct ice_hw *hw, s32 adj, bool lock_sbq)
cycles = -(((s64)-adj) << 32);
for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
- int status;
+ int err;
- status = ice_ptp_prep_port_adj_e822(hw, port, cycles,
- lock_sbq);
- if (status)
- return status;
+ err = ice_ptp_prep_port_adj_e822(hw, port, cycles, lock_sbq);
+ if (err)
+ return err;
}
return 0;
@@ -3075,23 +3064,23 @@ ice_ptp_prep_phy_adj_e822(struct ice_hw *hw, s32 adj, bool lock_sbq)
static int
ice_ptp_prep_phy_incval_e822(struct ice_hw *hw, u64 incval)
{
- int status;
+ int err;
u8 port;
for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
- status = ice_write_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L,
- incval);
- if (status)
+ err = ice_write_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L,
+ incval);
+ if (err)
goto exit_err;
}
return 0;
exit_err:
- ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, status %d\n",
- port, status);
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n",
+ port, err);
- return status;
+ return err;
}
/**
@@ -3105,13 +3094,13 @@ ice_ptp_prep_phy_incval_e822(struct ice_hw *hw, u64 incval)
int
ice_ptp_read_phy_incval_e822(struct ice_hw *hw, u8 port, u64 *incval)
{
- int status;
+ int err;
- status = ice_read_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L, incval);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read TIMETUS_L, status %d\n",
- status);
- return status;
+ err = ice_read_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L, incval);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read TIMETUS_L, err %d\n",
+ err);
+ return err;
}
ice_debug(hw, ICE_DBG_PTP, "read INCVAL = 0x%016llx\n",
@@ -3136,47 +3125,47 @@ ice_ptp_read_phy_incval_e822(struct ice_hw *hw, u8 port, u64 *incval)
static int
ice_ptp_prep_phy_adj_target_e822(struct ice_hw *hw, u32 target_time)
{
- int status;
+ int err;
u8 port;
for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
/* Tx case */
/* No sub-nanoseconds data */
- status = ice_write_phy_reg_e822_lp(hw, port,
- P_REG_TX_TIMER_CNT_ADJ_L,
- 0, true);
- if (status)
+ err = ice_write_phy_reg_e822_lp(hw, port,
+ P_REG_TX_TIMER_CNT_ADJ_L,
+ 0, true);
+ if (err)
goto exit_err;
- status = ice_write_phy_reg_e822_lp(hw, port,
- P_REG_TX_TIMER_CNT_ADJ_U,
- target_time, true);
- if (status)
+ err = ice_write_phy_reg_e822_lp(hw, port,
+ P_REG_TX_TIMER_CNT_ADJ_U,
+ target_time, true);
+ if (err)
goto exit_err;
/* Rx case */
/* No sub-nanoseconds data */
- status = ice_write_phy_reg_e822_lp(hw, port,
- P_REG_RX_TIMER_CNT_ADJ_L,
- 0, true);
- if (status)
+ err = ice_write_phy_reg_e822_lp(hw, port,
+ P_REG_RX_TIMER_CNT_ADJ_L,
+ 0, true);
+ if (err)
goto exit_err;
- status = ice_write_phy_reg_e822_lp(hw, port,
- P_REG_RX_TIMER_CNT_ADJ_U,
- target_time, true);
- if (status)
+ err = ice_write_phy_reg_e822_lp(hw, port,
+ P_REG_RX_TIMER_CNT_ADJ_U,
+ target_time, true);
+ if (err)
goto exit_err;
}
return 0;
exit_err:
- ice_debug(hw, ICE_DBG_PTP, "Failed to write target time for port %u, status %d\n",
- port, status);
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write target time for port %u, err %d\n",
+ port, err);
- return status;
+ return err;
}
/**
@@ -3194,25 +3183,25 @@ int
ice_ptp_read_port_capture_e822(struct ice_hw *hw, u8 port, u64 *tx_ts,
u64 *rx_ts)
{
- int status;
+ int err;
/* Tx case */
- status = ice_read_64b_phy_reg_e822(hw, port, P_REG_TX_CAPTURE_L, tx_ts);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, status %d\n",
- status);
- return status;
+ err = ice_read_64b_phy_reg_e822(hw, port, P_REG_TX_CAPTURE_L, tx_ts);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n",
+ err);
+ return err;
}
ice_debug(hw, ICE_DBG_PTP, "tx_init = 0x%016llx\n",
(unsigned long long)*tx_ts);
/* Rx case */
- status = ice_read_64b_phy_reg_e822(hw, port, P_REG_RX_CAPTURE_L, rx_ts);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, status %d\n",
- status);
- return status;
+ err = ice_read_64b_phy_reg_e822(hw, port, P_REG_RX_CAPTURE_L, rx_ts);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n",
+ err);
+ return err;
}
ice_debug(hw, ICE_DBG_PTP, "rx_init = 0x%016llx\n",
@@ -3238,24 +3227,24 @@ ice_ptp_write_port_cmd_e822(struct ice_hw *hw, u8 port,
enum ice_ptp_tmr_cmd cmd, bool lock_sbq)
{
u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd);
- int status;
+ int err;
/* Tx case */
- status = ice_write_phy_reg_e822_lp(hw, port, P_REG_TX_TMR_CMD, val,
- lock_sbq);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, status %d\n",
- status);
- return status;
+ err = ice_write_phy_reg_e822_lp(hw, port, P_REG_TX_TMR_CMD, val,
+ lock_sbq);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n",
+ err);
+ return err;
}
/* Rx case */
- status = ice_write_phy_reg_e822_lp(hw, port, P_REG_RX_TMR_CMD, val,
- lock_sbq);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, status %d\n",
- status);
- return status;
+ err = ice_write_phy_reg_e822_lp(hw, port, P_REG_RX_TMR_CMD, val,
+ lock_sbq);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n",
+ err);
+ return err;
}
return 0;
@@ -3285,13 +3274,13 @@ ice_phy_get_speed_and_fec_e822(struct ice_hw *hw, u8 port,
{
enum ice_ptp_link_spd link;
enum ice_ptp_fec_mode fec;
- int status;
u32 serdes;
+ int err;
- status = ice_read_phy_reg_e822(hw, port, P_REG_LINK_SPEED, &serdes);
- if (status) {
+ err = ice_read_phy_reg_e822(hw, port, P_REG_LINK_SPEED, &serdes);
+ if (err) {
ice_debug(hw, ICE_DBG_PTP, "Failed to read serdes info\n");
- return status;
+ return err;
}
/* Determine the FEC algorithm */
@@ -3352,23 +3341,23 @@ ice_phy_get_speed_and_fec_e822(struct ice_hw *hw, u8 port,
void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port)
{
enum ice_ptp_link_spd link_spd;
- int status;
+ int err;
u32 val;
u8 quad;
- status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, NULL);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to get PHY link speed, status %d\n",
- status);
+ err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, NULL);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to get PHY link speed, err %d\n",
+ err);
return;
}
quad = port / ICE_PORTS_PER_QUAD;
- status = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEM_GLB_CFG, status %d\n",
- status);
+ err = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEM_GLB_CFG, err %d\n",
+ err);
return;
}
@@ -3377,10 +3366,10 @@ void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port)
else
val |= Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M;
- status = ice_write_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG, val);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_MEM_GBL_CFG, status %d\n",
- status);
+ err = ice_write_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG, val);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_MEM_GBL_CFG, err %d\n",
+ err);
return;
}
}
@@ -3434,7 +3423,7 @@ void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port)
static int ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port)
{
u64 cur_freq, clk_incval, tu_per_sec, uix;
- int status;
+ int err;
cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));
clk_incval = ice_ptp_read_src_incval(hw);
@@ -3448,23 +3437,23 @@ static int ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port)
/* Program the 10Gb/40Gb conversion ratio */
uix = DIV_U64(tu_per_sec * LINE_UI_10G_40G, 390625000);
- status = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_10G_40G_L,
- uix);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_10G_40G, status %d\n",
- status);
- return status;
+ err = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_10G_40G_L,
+ uix);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_10G_40G, err %d\n",
+ err);
+ return err;
}
/* Program the 25Gb/100Gb conversion ratio */
uix = DIV_U64(tu_per_sec * LINE_UI_25G_100G, 390625000);
- status = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_25G_100G_L,
- uix);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_25G_100G, status %d\n",
- status);
- return status;
+ err = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_25G_100G_L,
+ uix);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_25G_100G, err %d\n",
+ err);
+ return err;
}
return 0;
@@ -3518,11 +3507,11 @@ static int ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
u64 cur_freq, clk_incval, tu_per_sec, phy_tus;
enum ice_ptp_link_spd link_spd;
enum ice_ptp_fec_mode fec_mode;
- int status;
+ int err;
- status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
- if (status)
- return status;
+ err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
+ if (err)
+ return err;
cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));
clk_incval = ice_ptp_read_src_incval(hw);
@@ -3544,10 +3533,10 @@ static int ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
else
phy_tus = 0;
- status = ice_write_40b_phy_reg_e822(hw, port, P_REG_PAR_TX_TUS_L,
- phy_tus);
- if (status)
- return status;
+ err = ice_write_40b_phy_reg_e822(hw, port, P_REG_PAR_TX_TUS_L,
+ phy_tus);
+ if (err)
+ return err;
/* P_REG_PAR_RX_TUS */
if (e822_vernier[link_spd].rx_par_clk)
@@ -3556,10 +3545,10 @@ static int ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
else
phy_tus = 0;
- status = ice_write_40b_phy_reg_e822(hw, port, P_REG_PAR_RX_TUS_L,
- phy_tus);
- if (status)
- return status;
+ err = ice_write_40b_phy_reg_e822(hw, port, P_REG_PAR_RX_TUS_L,
+ phy_tus);
+ if (err)
+ return err;
/* P_REG_PCS_TX_TUS */
if (e822_vernier[link_spd].tx_pcs_clk)
@@ -3568,10 +3557,10 @@ static int ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
else
phy_tus = 0;
- status = ice_write_40b_phy_reg_e822(hw, port, P_REG_PCS_TX_TUS_L,
- phy_tus);
- if (status)
- return status;
+ err = ice_write_40b_phy_reg_e822(hw, port, P_REG_PCS_TX_TUS_L,
+ phy_tus);
+ if (err)
+ return err;
/* P_REG_PCS_RX_TUS */
if (e822_vernier[link_spd].rx_pcs_clk)
@@ -3580,10 +3569,10 @@ static int ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
else
phy_tus = 0;
- status = ice_write_40b_phy_reg_e822(hw, port, P_REG_PCS_RX_TUS_L,
- phy_tus);
- if (status)
- return status;
+ err = ice_write_40b_phy_reg_e822(hw, port, P_REG_PCS_RX_TUS_L,
+ phy_tus);
+ if (err)
+ return err;
/* P_REG_DESK_PAR_TX_TUS */
if (e822_vernier[link_spd].tx_desk_rsgb_par)
@@ -3592,10 +3581,10 @@ static int ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
else
phy_tus = 0;
- status = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PAR_TX_TUS_L,
- phy_tus);
- if (status)
- return status;
+ err = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PAR_TX_TUS_L,
+ phy_tus);
+ if (err)
+ return err;
/* P_REG_DESK_PAR_RX_TUS */
if (e822_vernier[link_spd].rx_desk_rsgb_par)
@@ -3604,10 +3593,10 @@ static int ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
else
phy_tus = 0;
- status = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PAR_RX_TUS_L,
- phy_tus);
- if (status)
- return status;
+ err = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PAR_RX_TUS_L,
+ phy_tus);
+ if (err)
+ return err;
/* P_REG_DESK_PCS_TX_TUS */
if (e822_vernier[link_spd].tx_desk_rsgb_pcs)
@@ -3616,10 +3605,10 @@ static int ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
else
phy_tus = 0;
- status = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PCS_TX_TUS_L,
- phy_tus);
- if (status)
- return status;
+ err = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PCS_TX_TUS_L,
+ phy_tus);
+ if (err)
+ return err;
/* P_REG_DESK_PCS_RX_TUS */
if (e822_vernier[link_spd].rx_desk_rsgb_pcs)
@@ -3685,12 +3674,12 @@ int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port)
{
enum ice_ptp_link_spd link_spd;
enum ice_ptp_fec_mode fec_mode;
- int status;
u64 total_offset, val;
+ int err;
- status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
- if (status)
- return status;
+ err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
+ if (err)
+ return err;
total_offset = ice_calc_fixed_tx_offset_e822(hw, link_spd);
@@ -3703,11 +3692,11 @@ int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port)
link_spd == ICE_PTP_LNK_SPD_25G_RS ||
link_spd == ICE_PTP_LNK_SPD_40G ||
link_spd == ICE_PTP_LNK_SPD_50G) {
- status = ice_read_64b_phy_reg_e822(hw, port,
- P_REG_PAR_PCS_TX_OFFSET_L,
- &val);
- if (status)
- return status;
+ err = ice_read_64b_phy_reg_e822(hw, port,
+ P_REG_PAR_PCS_TX_OFFSET_L,
+ &val);
+ if (err)
+ return err;
total_offset += val;
}
@@ -3718,11 +3707,10 @@ int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port)
*/
if (link_spd == ICE_PTP_LNK_SPD_50G_RS ||
link_spd == ICE_PTP_LNK_SPD_100G_RS) {
- status = ice_read_64b_phy_reg_e822(hw, port,
- P_REG_PAR_TX_TIME_L,
- &val);
- if (status)
- return status;
+ err = ice_read_64b_phy_reg_e822(hw, port, P_REG_PAR_TX_TIME_L,
+ &val);
+ if (err)
+ return err;
total_offset += val;
}
@@ -3731,14 +3719,14 @@ int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port)
* PHY and indicate that the Tx offset is ready. After this,
* timestamps will be enabled.
*/
- status = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_TX_OFFSET_L,
- total_offset);
- if (status)
- return status;
+ err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_TX_OFFSET_L,
+ total_offset);
+ if (err)
+ return err;
- status = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 1);
- if (status)
- return status;
+ err = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 1);
+ if (err)
+ return err;
return 0;
}
@@ -3756,12 +3744,12 @@ ice_phy_cfg_fixed_tx_offset_e822(struct ice_hw *hw, u8 port)
{
enum ice_ptp_link_spd link_spd;
enum ice_ptp_fec_mode fec_mode;
- int status;
+ int err;
u64 total_offset;
- status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
- if (status)
- return status;
+ err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
+ if (err)
+ return err;
total_offset = ice_calc_fixed_tx_offset_e822(hw, link_spd);
@@ -3772,14 +3760,14 @@ ice_phy_cfg_fixed_tx_offset_e822(struct ice_hw *hw, u8 port)
* Note that this skips including the more precise offsets generated
* by the Vernier calibration.
*/
- status = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_TX_OFFSET_L,
+ err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_TX_OFFSET_L,
total_offset);
- if (status)
- return status;
+ if (err)
+ return err;
- status = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 1);
- if (status)
- return status;
+ err = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 1);
+ if (err)
+ return err;
return 0;
}
@@ -3803,14 +3791,14 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,
{
u64 cur_freq, clk_incval, tu_per_sec, mult, adj;
u32 pmd_adj_divisor, val;
- int status;
+ int err;
u8 pmd_align;
- status = ice_read_phy_reg_e822(hw, port, P_REG_PMD_ALIGNMENT, &val);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read PMD alignment, status %d\n",
- status);
- return status;
+ err = ice_read_phy_reg_e822(hw, port, P_REG_PMD_ALIGNMENT, &val);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read PMD alignment, err %d\n",
+ err);
+ return err;
}
pmd_align = (u8)val;
@@ -3897,12 +3885,12 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,
u64 cycle_adj;
u8 rx_cycle;
- status = ice_read_phy_reg_e822(hw, port, P_REG_RX_40_TO_160_CNT,
- &val);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read 25G-RS Rx cycle count, status %d\n",
- status);
- return status;
+ err = ice_read_phy_reg_e822(hw, port, P_REG_RX_40_TO_160_CNT,
+ &val);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read 25G-RS Rx cycle count, err %d\n",
+ err);
+ return err;
}
rx_cycle = val & P_REG_RX_40_TO_160_CNT_RXCYC_M;
@@ -3919,12 +3907,12 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,
u64 cycle_adj;
u8 rx_cycle;
- status = ice_read_phy_reg_e822(hw, port, P_REG_RX_80_TO_160_CNT,
- &val);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read 50G-RS Rx cycle count, status %d\n",
- status);
- return status;
+ err = ice_read_phy_reg_e822(hw, port, P_REG_RX_80_TO_160_CNT,
+ &val);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read 50G-RS Rx cycle count, err %d\n",
+ err);
+ return err;
}
rx_cycle = val & P_REG_RX_80_TO_160_CNT_RXCYC_M;
@@ -4000,22 +3988,22 @@ int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port)
enum ice_ptp_link_spd link_spd;
enum ice_ptp_fec_mode fec_mode;
u64 total_offset, pmd, val;
- int status;
+ int err;
- status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
- if (status)
- return status;
+ err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
+ if (err)
+ return err;
total_offset = ice_calc_fixed_rx_offset_e822(hw, link_spd);
/* Read the first Vernier offset from the PHY register and add it to
* the total offset.
*/
- status = ice_read_64b_phy_reg_e822(hw, port,
- P_REG_PAR_PCS_RX_OFFSET_L,
- &val);
- if (status)
- return status;
+ err = ice_read_64b_phy_reg_e822(hw, port,
+ P_REG_PAR_PCS_RX_OFFSET_L,
+ &val);
+ if (err)
+ return err;
total_offset += val;
@@ -4026,19 +4014,19 @@ int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port)
link_spd == ICE_PTP_LNK_SPD_50G ||
link_spd == ICE_PTP_LNK_SPD_50G_RS ||
link_spd == ICE_PTP_LNK_SPD_100G_RS) {
- status = ice_read_64b_phy_reg_e822(hw, port,
- P_REG_PAR_RX_TIME_L,
- &val);
- if (status)
- return status;
+ err = ice_read_64b_phy_reg_e822(hw, port,
+ P_REG_PAR_RX_TIME_L,
+ &val);
+ if (err)
+ return err;
total_offset += val;
}
/* In addition, Rx must account for the PMD alignment */
- status = ice_phy_calc_pmd_adj_e822(hw, port, link_spd, fec_mode, &pmd);
- if (status)
- return status;
+ err = ice_phy_calc_pmd_adj_e822(hw, port, link_spd, fec_mode, &pmd);
+ if (err)
+ return err;
/* For RS-FEC, this adjustment adds delay, but for other modes, it
* subtracts delay.
@@ -4052,14 +4040,14 @@ int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port)
* PHY and indicate that the Rx offset is ready. After this,
* timestamps will be enabled.
*/
- status = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_RX_OFFSET_L,
- total_offset);
- if (status)
- return status;
+ err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_RX_OFFSET_L,
+ total_offset);
+ if (err)
+ return err;
- status = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 1);
- if (status)
- return status;
+ err = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 1);
+ if (err)
+ return err;
return 0;
}
@@ -4077,12 +4065,12 @@ ice_phy_cfg_fixed_rx_offset_e822(struct ice_hw *hw, u8 port)
{
enum ice_ptp_link_spd link_spd;
enum ice_ptp_fec_mode fec_mode;
- int status;
+ int err;
u64 total_offset;
- status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
- if (status)
- return status;
+ err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
+ if (err)
+ return err;
total_offset = ice_calc_fixed_rx_offset_e822(hw, link_spd);
@@ -4093,14 +4081,14 @@ ice_phy_cfg_fixed_rx_offset_e822(struct ice_hw *hw, u8 port)
* Note that this skips including the more precise offsets generated
* by Vernier calibration.
*/
- status = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_RX_OFFSET_L,
+ err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_RX_OFFSET_L,
total_offset);
- if (status)
- return status;
+ if (err)
+ return err;
- status = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 1);
- if (status)
- return status;
+ err = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 1);
+ if (err)
+ return err;
return 0;
}
@@ -4119,10 +4107,10 @@ static int
ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8 port, u64 *phy_time,
u64 *phc_time)
{
- int status;
u64 tx_time, rx_time;
u32 zo, lo;
u8 tmr_idx;
+ int err;
tmr_idx = ice_get_ptp_src_clock_index(hw);
@@ -4130,9 +4118,9 @@ ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8 port, u64 *phy_time,
ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME);
/* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */
- status = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME, true);
- if (status)
- return status;
+ err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME, true);
+ if (err)
+ return err;
/* Issue the sync to start the ICE_PTP_READ_TIME capture */
ice_ptp_exec_tmr_cmd(hw);
@@ -4143,9 +4131,9 @@ ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8 port, u64 *phy_time,
*phc_time = (u64)lo << 32 | zo;
/* Read the captured PHY time from the PHY shadow registers */
- status = ice_ptp_read_port_capture_e822(hw, port, &tx_time, &rx_time);
- if (status)
- return status;
+ err = ice_ptp_read_port_capture_e822(hw, port, &tx_time, &rx_time);
+ if (err)
+ return err;
/* If the PHY Tx and Rx timers don't match, log a warning message.
* Note that this should not happen in normal circumstances since the
@@ -4176,15 +4164,15 @@ ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8 port, u64 *phy_time,
static int ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port)
{
u64 phc_time, phy_time, difference;
- int status;
+ int err;
if (!ice_ptp_lock(hw)) {
ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n");
return ICE_ERR_NOT_READY;
}
- status = ice_read_phy_and_phc_time_e822(hw, port, &phy_time, &phc_time);
- if (status)
+ err = ice_read_phy_and_phc_time_e822(hw, port, &phy_time, &phc_time);
+ if (err)
goto err_unlock;
/* Calculate the amount required to add to the port time in order for
@@ -4197,12 +4185,12 @@ static int ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port)
*/
difference = phc_time - phy_time;
- status = ice_ptp_prep_port_adj_e822(hw, port, (s64)difference, true);
- if (status)
+ err = ice_ptp_prep_port_adj_e822(hw, port, (s64)difference, true);
+ if (err)
goto err_unlock;
- status = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME, true);
- if (status)
+ err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME, true);
+ if (err)
goto err_unlock;
/* Do not perform any action on the main timer */
@@ -4214,8 +4202,8 @@ static int ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port)
/* Re-capture the timer values to flush the command registers and
* verify that the time was properly adjusted.
*/
- status = ice_read_phy_and_phc_time_e822(hw, port, &phy_time, &phc_time);
- if (status)
+ err = ice_read_phy_and_phc_time_e822(hw, port, &phy_time, &phc_time);
+ if (err)
goto err_unlock;
ice_info(hw, "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n",
@@ -4228,7 +4216,7 @@ static int ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port)
err_unlock:
ice_ptp_unlock(hw);
- return status;
+ return err;
}
/**
@@ -4244,36 +4232,36 @@ static int ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port)
int
ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset)
{
- int status;
+ int err;
u32 val;
- status = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 0);
- if (status)
- return status;
+ err = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 0);
+ if (err)
+ return err;
- status = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 0);
- if (status)
- return status;
+ err = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 0);
+ if (err)
+ return err;
- status = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val);
- if (status)
- return status;
+ err = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val);
+ if (err)
+ return err;
val &= ~P_REG_PS_START_M;
- status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
- if (status)
- return status;
+ err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
+ if (err)
+ return err;
val &= ~P_REG_PS_ENA_CLK_M;
- status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
- if (status)
- return status;
+ err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
+ if (err)
+ return err;
if (soft_reset) {
val |= P_REG_PS_SFT_RESET_M;
- status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
- if (status)
- return status;
+ err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
+ if (err)
+ return err;
}
ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port);
@@ -4300,101 +4288,101 @@ ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset)
int
ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass)
{
- int status;
u32 lo, hi, val;
u64 incval;
u8 tmr_idx;
+ int err;
tmr_idx = ice_get_ptp_src_clock_index(hw);
- status = ice_stop_phy_timer_e822(hw, port, false);
- if (status)
- return status;
+ err = ice_stop_phy_timer_e822(hw, port, false);
+ if (err)
+ return err;
ice_phy_cfg_lane_e822(hw, port);
- status = ice_phy_cfg_uix_e822(hw, port);
- if (status)
- return status;
+ err = ice_phy_cfg_uix_e822(hw, port);
+ if (err)
+ return err;
- status = ice_phy_cfg_parpcs_e822(hw, port);
- if (status)
- return status;
+ err = ice_phy_cfg_parpcs_e822(hw, port);
+ if (err)
+ return err;
lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx));
hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));
incval = (u64)hi << 32 | lo;
- status = ice_write_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L, incval);
- if (status)
- return status;
+ err = ice_write_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L, incval);
+ if (err)
+ return err;
- status = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL, true);
- if (status)
- return status;
+ err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL, true);
+ if (err)
+ return err;
/* Do not perform any action on the main timer */
ice_ptp_src_cmd(hw, ICE_PTP_NOP);
ice_ptp_exec_tmr_cmd(hw);
- status = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val);
- if (status)
- return status;
+ err = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val);
+ if (err)
+ return err;
val |= P_REG_PS_SFT_RESET_M;
- status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
- if (status)
- return status;
+ err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
+ if (err)
+ return err;
val |= P_REG_PS_START_M;
- status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
- if (status)
- return status;
+ err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
+ if (err)
+ return err;
val &= ~P_REG_PS_SFT_RESET_M;
- status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
- if (status)
- return status;
+ err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
+ if (err)
+ return err;
- status = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL, true);
- if (status)
- return status;
+ err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL, true);
+ if (err)
+ return err;
ice_ptp_exec_tmr_cmd(hw);
val |= P_REG_PS_ENA_CLK_M;
- status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
- if (status)
- return status;
+ err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
+ if (err)
+ return err;
val |= P_REG_PS_LOAD_OFFSET_M;
- status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
- if (status)
- return status;
+ err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
+ if (err)
+ return err;
ice_ptp_exec_tmr_cmd(hw);
- status = ice_sync_phy_timer_e822(hw, port);
- if (status)
- return status;
+ err = ice_sync_phy_timer_e822(hw, port);
+ if (err)
+ return err;
if (bypass) {
val |= P_REG_PS_BYPASS_MODE_M;
/* Enter BYPASS mode, enabling timestamps immediately. */
- status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
- if (status)
- return status;
+ err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
+ if (err)
+ return err;
/* Program the fixed Tx offset */
- status = ice_phy_cfg_fixed_tx_offset_e822(hw, port);
- if (status)
- return status;
+ err = ice_phy_cfg_fixed_tx_offset_e822(hw, port);
+ if (err)
+ return err;
/* Program the fixed Rx offset */
- status = ice_phy_cfg_fixed_rx_offset_e822(hw, port);
- if (status)
- return status;
+ err = ice_phy_cfg_fixed_rx_offset_e822(hw, port);
+ if (err)
+ return err;
}
ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port);
@@ -4418,14 +4406,14 @@ ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass)
*/
int ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port)
{
- int status;
+ int err;
u32 val;
- status = ice_read_phy_reg_e822(hw, port, P_REG_TX_OV_STATUS, &val);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, status %d\n",
- port, status);
- return status;
+ err = ice_read_phy_reg_e822(hw, port, P_REG_TX_OV_STATUS, &val);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, err %d\n",
+ port, err);
+ return err;
}
if (!(val & P_REG_TX_OV_STATUS_OV_M)) {
@@ -4434,11 +4422,11 @@ int ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port)
return ICE_ERR_NOT_READY;
}
- status = ice_read_phy_reg_e822(hw, port, P_REG_RX_OV_STATUS, &val);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, status %d\n",
- port, status);
- return status;
+ err = ice_read_phy_reg_e822(hw, port, P_REG_RX_OV_STATUS, &val);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, err %d\n",
+ port, err);
+ return err;
}
if (!(val & P_REG_TX_OV_STATUS_OV_M)) {
@@ -4447,26 +4435,26 @@ int ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port)
return ICE_ERR_NOT_READY;
}
- status = ice_phy_cfg_tx_offset_e822(hw, port);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to program total Tx offset for port %u, status %d\n",
- port, status);
- return status;
+ err = ice_phy_cfg_tx_offset_e822(hw, port);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to program total Tx offset for port %u, err %d\n",
+ port, err);
+ return err;
}
- status = ice_phy_cfg_rx_offset_e822(hw, port);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to program total Rx offset for port %u, status %d\n",
- port, status);
- return status;
+ err = ice_phy_cfg_rx_offset_e822(hw, port);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to program total Rx offset for port %u, err %d\n",
+ port, err);
+ return err;
}
/* Exit bypass mode now that the offset has been updated */
- status = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read P_REG_PS for port %u, status %d\n",
- port, status);
- return status;
+ err = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read P_REG_PS for port %u, err %d\n",
+ port, err);
+ return err;
}
if (!(val & P_REG_PS_BYPASS_MODE_M))
@@ -4474,11 +4462,11 @@ int ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port)
port);
val &= ~P_REG_PS_BYPASS_MODE_M;
- status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to disable bypass for port %u, status %d\n",
- port, status);
- return status;
+ err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to disable bypass for port %u, err %d\n",
+ port, err);
+ return err;
}
ice_info(hw, "Exiting bypass mode on PHY port %u\n", port);
@@ -4505,18 +4493,18 @@ static int
ice_read_phy_reg_e810_lp(struct ice_hw *hw, u32 addr, u32 *val, bool lock_sbq)
{
struct ice_sbq_msg_input msg = {0};
- int status;
+ int err;
msg.msg_addr_low = ICE_LO_WORD(addr);
msg.msg_addr_high = ICE_HI_WORD(addr);
msg.opcode = ice_sbq_msg_rd;
msg.dest_dev = rmn_0;
- status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n",
- status);
- return status;
+ err = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
+ err);
+ return err;
}
*val = msg.data;
@@ -4542,7 +4530,7 @@ static int
ice_write_phy_reg_e810_lp(struct ice_hw *hw, u32 addr, u32 val, bool lock_sbq)
{
struct ice_sbq_msg_input msg = {0};
- int status;
+ int err;
msg.msg_addr_low = ICE_LO_WORD(addr);
msg.msg_addr_high = ICE_HI_WORD(addr);
@@ -4550,11 +4538,11 @@ ice_write_phy_reg_e810_lp(struct ice_hw *hw, u32 addr, u32 val, bool lock_sbq)
msg.dest_dev = rmn_0;
msg.data = val;
- status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n",
- status);
- return status;
+ err = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
+ err);
+ return err;
}
return 0;
@@ -4623,21 +4611,21 @@ ice_read_phy_tstamp_sbq_e810(struct ice_hw *hw, u8 lport, u8 idx, u8 *hi,
{
u32 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx);
u32 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx);
- int status;
u32 lo_val, hi_val;
+ int err;
- status = ice_read_phy_reg_e810(hw, lo_addr, &lo_val);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, status %d\n",
- status);
- return status;
+ err = ice_read_phy_reg_e810(hw, lo_addr, &lo_val);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n",
+ err);
+ return err;
}
- status = ice_read_phy_reg_e810(hw, hi_addr, &hi_val);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, status %d\n",
- status);
- return status;
+ err = ice_read_phy_reg_e810(hw, hi_addr, &hi_val);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n",
+ err);
+ return err;
}
*lo = lo_val;
@@ -4659,17 +4647,17 @@ ice_read_phy_tstamp_sbq_e810(struct ice_hw *hw, u8 lport, u8 idx, u8 *hi,
static int
ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp)
{
- int status;
u32 lo = 0;
u8 hi = 0;
+ int err;
if (hw->dev_caps.ts_dev_info.ts_ll_read)
- status = ice_read_phy_tstamp_ll_e810(hw, idx, &hi, &lo);
+ err = ice_read_phy_tstamp_ll_e810(hw, idx, &hi, &lo);
else
- status = ice_read_phy_tstamp_sbq_e810(hw, lport, idx, &hi, &lo);
+ err = ice_read_phy_tstamp_sbq_e810(hw, lport, idx, &hi, &lo);
- if (status)
- return status;
+ if (err)
+ return err;
/* For E810 devices, the timestamp is reported with the lower 32 bits
* in the low register, and the upper 8 bits in the high register.
@@ -4686,7 +4674,7 @@ ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp)
* @idx: the timestamp index to reset
*
* Clear a timestamp from the timestamp block, discarding its value without
- * returning it. This resets the memory status bit for the timestamp index
+ * returning it. This resets the memory err bit for the timestamp index
* allowing it to be reused for another timestamp in the future.
*
* For E822 devices, the block number is the PHY quad to clear from. For E810
@@ -4698,24 +4686,24 @@ ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp)
static int
ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx)
{
- int status;
+ int err;
u32 lo_addr, hi_addr;
lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx);
hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx);
- status = ice_write_phy_reg_e810(hw, lo_addr, 0);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, status %d\n",
- status);
- return status;
+ err = ice_write_phy_reg_e810(hw, lo_addr, 0);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, err %d\n",
+ err);
+ return err;
}
- status = ice_write_phy_reg_e810(hw, hi_addr, 0);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, status %d\n",
- status);
- return status;
+ err = ice_write_phy_reg_e810(hw, hi_addr, 0);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, err %d\n",
+ err);
+ return err;
}
return 0;
@@ -4732,17 +4720,17 @@ ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx)
*/
int ice_ptp_init_phy_e810(struct ice_hw *hw)
{
- int status;
u8 tmr_idx;
+ int err;
tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
- status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_ENA(tmr_idx),
- GLTSYN_ENA_TSYN_ENA_M);
- if (status)
+ err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_ENA(tmr_idx),
+ GLTSYN_ENA_TSYN_ENA_M);
+ if (err)
ice_debug(hw, ICE_DBG_PTP, "PTP failed in ena_phy_time_syn %d\n",
- status);
+ err);
- return status;
+ return err;
}
/**
@@ -4774,22 +4762,22 @@ static int ice_ptp_init_phc_e810(struct ice_hw *hw)
*/
static int ice_ptp_prep_phy_time_e810(struct ice_hw *hw, u32 time)
{
- int status;
u8 tmr_idx;
+ int err;
tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
- status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_0, status %d\n",
- status);
- return status;
+ err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_0, err %d\n",
+ err);
+ return err;
}
- status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx), time);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_L, status %d\n",
- status);
- return status;
+ err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx), time);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_L, err %d\n",
+ err);
+ return err;
}
return 0;
@@ -4812,28 +4800,28 @@ static int ice_ptp_prep_phy_time_e810(struct ice_hw *hw, u32 time)
static int
ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj, bool lock_sbq)
{
- int status;
u8 tmr_idx;
+ int err;
tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
/* Adjustments are represented as signed 2's complement values in
* nanoseconds. Sub-nanosecond adjustment is not supported.
*/
- status = ice_write_phy_reg_e810_lp(hw, ETH_GLTSYN_SHADJ_L(tmr_idx),
- 0, lock_sbq);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_L, status %d\n",
- status);
- return status;
+ err = ice_write_phy_reg_e810_lp(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), 0,
+ lock_sbq);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_L, err %d\n",
+ err);
+ return err;
}
- status = ice_write_phy_reg_e810_lp(hw, ETH_GLTSYN_SHADJ_H(tmr_idx),
- adj, lock_sbq);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_H, status %d\n",
- status);
- return status;
+ err = ice_write_phy_reg_e810_lp(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), adj,
+ lock_sbq);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_H, err %d\n",
+ err);
+ return err;
}
return 0;
@@ -4851,26 +4839,26 @@ ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj, bool lock_sbq)
static int
ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval)
{
- int status;
u32 high, low;
u8 tmr_idx;
+ int err;
tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
low = ICE_LO_DWORD(incval);
high = ICE_HI_DWORD(incval);
- status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), low);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write incval to PHY SHADJ_L, status %d\n",
- status);
- return status;
+ err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), low);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write incval to PHY SHADJ_L, err %d\n",
+ err);
+ return err;
}
- status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), high);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write incval PHY SHADJ_H, status %d\n",
- status);
- return status;
+ err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), high);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write incval PHY SHADJ_H, err %d\n",
+ err);
+ return err;
}
return 0;
@@ -4893,23 +4881,23 @@ ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval)
static int
ice_ptp_prep_phy_adj_target_e810(struct ice_hw *hw, u32 target_time)
{
- int status;
+ int err;
u8 tmr_idx;
tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
- status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write target time to SHTIME_0, status %d\n",
- status);
- return status;
+ err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write target time to SHTIME_0, err %d\n",
+ err);
+ return err;
}
- status = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx),
- target_time);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write target time to SHTIME_L, status %d\n",
- status);
- return status;
+ err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx),
+ target_time);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write target time to SHTIME_L, err %d\n",
+ err);
+ return err;
}
return 0;
@@ -5378,16 +5366,16 @@ int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port,
for (port = 0; port < hw->max_phy_port; port++) {
enum ice_ptp_tmr_cmd cmd;
- int status;
+ int err;
/* Program the configured port with the configured command,
* program all other ports with ICE_PTP_NOP.
*/
cmd = port == configured_port ? configured_cmd : ICE_PTP_NOP;
- status = ice_ptp_write_port_cmd(hw, port, cmd, lock_sbq);
- if (status)
- return status;
+ err = ice_ptp_write_port_cmd(hw, port, cmd, lock_sbq);
+ if (err)
+ return err;
}
return 0;
@@ -5420,11 +5408,11 @@ static int ice_ptp_port_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
/* PHY models which require programming each port separately */
for (port = 0; port < hw->max_phy_port; port++) {
- int status;
+ int err;
- status = ice_ptp_write_port_cmd(hw, port, cmd, lock_sbq);
- if (status)
- return status;
+ err = ice_ptp_write_port_cmd(hw, port, cmd, lock_sbq);
+ if (err)
+ return err;
}
return 0;
@@ -5444,17 +5432,17 @@ static int ice_ptp_port_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
bool lock_sbq)
{
- int status;
+ int err;
/* First, prepare the source timer */
ice_ptp_src_cmd(hw, cmd);
/* Next, prepare the ports */
- status = ice_ptp_port_cmd(hw, cmd, lock_sbq);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, status %d\n",
- cmd, status);
- return status;
+ err = ice_ptp_port_cmd(hw, cmd, lock_sbq);
+ if (err) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, err %d\n",
+ cmd, err);
+ return err;
}
/* Write the sync command register to drive both source and PHY timer
@@ -5480,7 +5468,7 @@ static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
*/
int ice_ptp_init_time(struct ice_hw *hw, u64 time)
{
- int status;
+ int err;
u8 tmr_idx;
tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
@@ -5498,20 +5486,20 @@ int ice_ptp_init_time(struct ice_hw *hw, u64 time)
/* Fill Rx and Tx ports and send msg to PHY */
switch (hw->phy_cfg) {
case ICE_PHY_ETH56G:
- status = ice_ptp_prep_phy_time_eth56g(hw, time & 0xFFFFFFFF);
+ err = ice_ptp_prep_phy_time_eth56g(hw, time & 0xFFFFFFFF);
break;
case ICE_PHY_E810:
- status = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF);
+ err = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF);
break;
case ICE_PHY_E822:
- status = ice_ptp_prep_phy_time_e822(hw, time & 0xFFFFFFFF);
+ err = ice_ptp_prep_phy_time_e822(hw, time & 0xFFFFFFFF);
break;
default:
- status = ICE_ERR_NOT_SUPPORTED;
+ err = ICE_ERR_NOT_SUPPORTED;
}
- if (status)
- return status;
+ if (err)
+ return err;
return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_TIME, true);
}
@@ -5532,7 +5520,7 @@ int ice_ptp_init_time(struct ice_hw *hw, u64 time)
*/
int ice_ptp_write_incval(struct ice_hw *hw, u64 incval)
{
- int status;
+ int err;
u8 tmr_idx;
tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
@@ -5547,20 +5535,20 @@ int ice_ptp_write_incval(struct ice_hw *hw, u64 incval)
switch (hw->phy_cfg) {
case ICE_PHY_ETH56G:
- status = ice_ptp_prep_phy_incval_eth56g(hw, incval);
+ err = ice_ptp_prep_phy_incval_eth56g(hw, incval);
break;
case ICE_PHY_E810:
- status = ice_ptp_prep_phy_incval_e810(hw, incval);
+ err = ice_ptp_prep_phy_incval_e810(hw, incval);
break;
case ICE_PHY_E822:
- status = ice_ptp_prep_phy_incval_e822(hw, incval);
+ err = ice_ptp_prep_phy_incval_e822(hw, incval);
break;
default:
- status = ICE_ERR_NOT_SUPPORTED;
+ err = ICE_ERR_NOT_SUPPORTED;
}
- if (status)
- return status;
+ if (err)
+ return err;
return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_INCVAL, true);
}
@@ -5574,16 +5562,16 @@ int ice_ptp_write_incval(struct ice_hw *hw, u64 incval)
*/
int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval)
{
- int status;
+ int err;
if (!ice_ptp_lock(hw))
return ICE_ERR_NOT_READY;
- status = ice_ptp_write_incval(hw, incval);
+ err = ice_ptp_write_incval(hw, incval);
ice_ptp_unlock(hw);
- return status;
+ return err;
}
/**
@@ -5603,7 +5591,7 @@ int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval)
*/
int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq)
{
- int status;
+ int err;
u8 tmr_idx;
tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
@@ -5618,23 +5606,23 @@ int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq)
switch (hw->phy_cfg) {
case ICE_PHY_ETH56G:
- status = ice_ptp_prep_phy_adj_eth56g(hw, adj, lock_sbq);
+ err = ice_ptp_prep_phy_adj_eth56g(hw, adj, lock_sbq);
break;
case ICE_PHY_E830:
/* E830 sync PHYs automatically after setting GLTSYN_SHADJ */
return 0;
case ICE_PHY_E810:
- status = ice_ptp_prep_phy_adj_e810(hw, adj, lock_sbq);
+ err = ice_ptp_prep_phy_adj_e810(hw, adj, lock_sbq);
break;
case ICE_PHY_E822:
- status = ice_ptp_prep_phy_adj_e822(hw, adj, lock_sbq);
+ err = ice_ptp_prep_phy_adj_e822(hw, adj, lock_sbq);
break;
default:
- status = ICE_ERR_NOT_SUPPORTED;
+ err = ICE_ERR_NOT_SUPPORTED;
}
- if (status)
- return status;
+ if (err)
+ return err;
return ice_ptp_tmr_cmd(hw, ICE_PTP_ADJ_TIME, lock_sbq);
}
@@ -5658,9 +5646,9 @@ int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq)
int
ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj)
{
- int status;
u32 time_lo, time_hi;
u8 tmr_idx;
+ int err;
tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
time_lo = ICE_LO_DWORD(at_time);
@@ -5682,38 +5670,38 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj)
/* Prepare PHY port adjustments */
switch (hw->phy_cfg) {
case ICE_PHY_ETH56G:
- status = ice_ptp_prep_phy_adj_eth56g(hw, adj, true);
+ err = ice_ptp_prep_phy_adj_eth56g(hw, adj, true);
break;
case ICE_PHY_E810:
- status = ice_ptp_prep_phy_adj_e810(hw, adj, true);
+ err = ice_ptp_prep_phy_adj_e810(hw, adj, true);
break;
case ICE_PHY_E822:
- status = ice_ptp_prep_phy_adj_e822(hw, adj, true);
+ err = ice_ptp_prep_phy_adj_e822(hw, adj, true);
break;
default:
- status = ICE_ERR_NOT_SUPPORTED;
+ err = ICE_ERR_NOT_SUPPORTED;
}
- if (status)
- return status;
+ if (err)
+ return err;
/* Set target time for each PHY port */
switch (hw->phy_cfg) {
case ICE_PHY_ETH56G:
- status = ice_ptp_prep_phy_adj_target_eth56g(hw, time_lo);
+ err = ice_ptp_prep_phy_adj_target_eth56g(hw, time_lo);
break;
case ICE_PHY_E810:
- status = ice_ptp_prep_phy_adj_target_e810(hw, time_lo);
+ err = ice_ptp_prep_phy_adj_target_e810(hw, time_lo);
break;
case ICE_PHY_E822:
- status = ice_ptp_prep_phy_adj_target_e822(hw, time_lo);
+ err = ice_ptp_prep_phy_adj_target_e822(hw, time_lo);
break;
default:
- status = ICE_ERR_NOT_SUPPORTED;
+ err = ICE_ERR_NOT_SUPPORTED;
}
- if (status)
- return status;
+ if (err)
+ return err;
return ice_ptp_tmr_cmd(hw, ICE_PTP_ADJ_TIME_AT_TIME, true);
}
@@ -5732,25 +5720,25 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj)
int
ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp)
{
- int status;
+ int err;
switch (hw->phy_cfg) {
case ICE_PHY_ETH56G:
- status = ice_read_phy_tstamp_eth56g(hw, block, idx, tstamp);
+ err = ice_read_phy_tstamp_eth56g(hw, block, idx, tstamp);
break;
case ICE_PHY_E830:
return ice_read_phy_tstamp_e830(hw, block, idx, tstamp);
case ICE_PHY_E810:
- status = ice_read_phy_tstamp_e810(hw, block, idx, tstamp);
+ err = ice_read_phy_tstamp_e810(hw, block, idx, tstamp);
break;
case ICE_PHY_E822:
- status = ice_read_phy_tstamp_e822(hw, block, idx, tstamp);
+ err = ice_read_phy_tstamp_e822(hw, block, idx, tstamp);
break;
default:
- status = ICE_ERR_NOT_SUPPORTED;
+ err = ICE_ERR_NOT_SUPPORTED;
}
- return status;
+ return err;
}
/**
@@ -5766,23 +5754,23 @@ ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp)
int
ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx)
{
- int status;
+ int err;
switch (hw->phy_cfg) {
case ICE_PHY_ETH56G:
- status = ice_clear_phy_tstamp_eth56g(hw, block, idx);
+ err = ice_clear_phy_tstamp_eth56g(hw, block, idx);
break;
case ICE_PHY_E810:
- status = ice_clear_phy_tstamp_e810(hw, block, idx);
+ err = ice_clear_phy_tstamp_e810(hw, block, idx);
break;
case ICE_PHY_E822:
- status = ice_clear_phy_tstamp_e822(hw, block, idx);
+ err = ice_clear_phy_tstamp_e822(hw, block, idx);
break;
default:
- status = ICE_ERR_NOT_SUPPORTED;
+ err = ICE_ERR_NOT_SUPPORTED;
}
- return status;
+ return err;
}
/**
@@ -5793,7 +5781,7 @@ ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx)
*/
int ice_ptp_init_phc(struct ice_hw *hw)
{
- int status;
+ int err;
u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned;
/* Enable source clocks */
@@ -5804,19 +5792,19 @@ int ice_ptp_init_phc(struct ice_hw *hw)
switch (hw->phy_cfg) {
case ICE_PHY_ETH56G:
- status = ice_ptp_init_phc_eth56g(hw);
+ err = ice_ptp_init_phc_eth56g(hw);
break;
case ICE_PHY_E810:
- status = ice_ptp_init_phc_e810(hw);
+ err = ice_ptp_init_phc_e810(hw);
break;
case ICE_PHY_E822:
- status = ice_ptp_init_phc_e822(hw);
+ err = ice_ptp_init_phc_e822(hw);
break;
default:
- status = ICE_ERR_NOT_SUPPORTED;
+ err = ICE_ERR_NOT_SUPPORTED;
}
- return status;
+ return err;
}
/**
--
2.43.0
next prev parent reply other threads:[~2024-06-12 15:14 UTC|newest]
Thread overview: 428+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-30 15:40 [RFC] net/ice: Update base code with latest snapshot Ian Stokes
2024-05-01 8:19 ` Thomas Monjalon
2024-05-01 9:06 ` Bruce Richardson
2024-05-01 12:08 ` Thomas Monjalon
2024-06-12 14:59 ` [PATCH v2 000/148] Update net/ice base driver to latest upstream snapshot Anatoly Burakov
2024-06-12 14:59 ` [PATCH v2 001/148] net/ice/base: convert enum ice_status to int Anatoly Burakov
2024-06-12 14:59 ` [PATCH v2 002/148] net/ice/base: replace ICE_SUCCESS with int Anatoly Burakov
2024-06-12 14:59 ` [PATCH v2 003/148] net/ice/base: update E830 headers Anatoly Burakov
2024-06-12 14:59 ` [PATCH v2 004/148] net/ice/base: update phy config during link restart Anatoly Burakov
2024-06-19 14:42 ` Bruce Richardson
2024-06-12 14:59 ` [PATCH v2 005/148] net/ice/base: fix for pointer to variable outside scope Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 006/148] net/ice/base: add missing include for flow Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 007/148] net/ice/base: add ability to set markid via switch filter Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 008/148] net/ice/base: improve ice_debug_cq messages Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 009/148] net/ice/base: add mgmt netlist auth support command Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 010/148] net/ice/base: fix undefined variables Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 011/148] net/ice/base: fix get media type Anatoly Burakov
2024-06-19 14:53 ` Bruce Richardson
2024-06-12 15:00 ` [PATCH v2 012/148] net/ice/base: clean up __ice_aq_get_set_rss_lut() Anatoly Burakov
2024-06-13 6:17 ` Przemek Kitszel
2024-06-21 12:31 ` Burakov, Anatoly
2024-06-19 14:55 ` Bruce Richardson
2024-06-12 15:00 ` [PATCH v2 013/148] net/ice/base: update flow seg fields to declared bitmaps Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 014/148] net/ice/base: update interface in ice_parse_common_caps Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 015/148] net/ice/base: refactor (non) bitmap declarations Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 016/148] net/ice/base: remove unnecessary control queue cmd_buf arrays Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 017/148] net/ice/base: alloc port_info only once Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 018/148] net/ice/base: update code with flex array safe allocations Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 019/148] net/ice/base: bring back ability to use 128 as size of PF type RSS LUT Anatoly Burakov
2024-06-19 15:51 ` Przemek Kitszel
2024-06-12 15:00 ` [PATCH v2 020/148] net/ice/base: support for OROM update in recovery mode Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 021/148] net/ice/base: code adjustments for E830 Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 022/148] net/ice/base: improve find recipe routine Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 023/148] net/ice/base: fix memory leak when checking firmware version Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 024/148] net/ice/base: add LL Tx timestamp interrupt read Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 025/148] net/ice/base: use model-dependent number of PHY ports Anatoly Burakov
2024-06-19 15:32 ` Bruce Richardson
2024-06-12 15:00 ` [PATCH v2 026/148] net/ice/base: use ice_bitmap_t in promisc functions Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 027/148] net/ice/base: fix rx-only unicast promiscuous mode Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 028/148] net/ice/base: add support for E825-C TX clock changing Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 029/148] net/ice/base: fix for applying multiple cloud filters Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 030/148] net/ice/base: limit PF RSS LUT to one VSI at time Anatoly Burakov
2024-06-19 15:41 ` Bruce Richardson
2024-06-19 15:53 ` Przemek Kitszel
2024-06-12 15:00 ` [PATCH v2 031/148] net/ice/base: prevent potential integer overflow Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 032/148] net/ice/base: cosmetic changes Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 033/148] net/ice/base: implement initial PTP support for E830 Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 034/148] net/ice/base: fix resource leak Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 035/148] net/ice/base: move lock outside of if-else Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 036/148] net/ice/base: refactor control queue send delay Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 037/148] net/ice/base: fix NVM feature check Anatoly Burakov
2024-06-20 10:28 ` Bruce Richardson
2024-06-12 15:00 ` [PATCH v2 038/148] net/ice/base: allow for dumping all clusters Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 039/148] net/ice/base: remove PTP aqc_driver_params Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 040/148] net/ice/base: add FW load status mask Anatoly Burakov
2024-06-20 10:29 ` Bruce Richardson
2024-06-12 15:00 ` [PATCH v2 041/148] net/ice/base: add direction metadata Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 042/148] net/ice/base: change data buffer in i2c write to be const Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 043/148] net/ice/base: remove unused code from upstream build Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 044/148] net/ice/base: fix sign-extension Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 045/148] net/ice/base: implement switch recipe reuse feature Anatoly Burakov
2024-06-18 14:53 ` Bruce Richardson
2024-06-12 15:00 ` [PATCH v2 046/148] net/ice/base: add helper function for refsync Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 047/148] net/ice/base: added informational message for NAC topology Anatoly Burakov
2024-06-20 12:02 ` Bruce Richardson
2024-06-12 15:00 ` [PATCH v2 048/148] net/ice/base: add Cage Max Power override NVM module Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 049/148] net/ice/base: adapt No FEC in Auto support check to add E82X devices Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 050/148] net/ice/base: move (read|write)_sma_ctrl functions to match upstream Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 051/148] net/ice/base: fix incorrect size when allocating children arrays Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 052/148] net/ice/base: fix GCS descriptor field offsets Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 053/148] net/ice/base: add VSI type for subfunctions Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 054/148] net/ice/base: correct the return type of ice_bitmap_hweight Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 055/148] net/ice/base: fix ice_ptp_one_port_cmd to avoid stale PHY commands Anatoly Burakov
2024-06-18 15:10 ` Bruce Richardson
2024-06-12 15:00 ` [PATCH v2 056/148] net/ice/base: remove dead code from ice_get_ddp_pkg_state Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 057/148] net/ice/base: get rid of enum ice_status Anatoly Burakov
2024-06-18 15:19 ` Bruce Richardson
2024-06-12 15:00 ` [PATCH v2 058/148] net/ice/base: use ICE_PTP_NOP to better indicate no action Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 059/148] net/ice/base: add fw log file Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 060/148] net/ice/base: update comments regarding clearing timestamps Anatoly Burakov
2024-06-12 15:00 ` Anatoly Burakov [this message]
2024-06-12 15:00 ` [PATCH v2 062/148] net/ice/base: re-number E810-T subdevice IDs to match upstream Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 063/148] net/ice/base: enable RDMA Act-Act unload paths Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 064/148] net/ice/base: parse 1PPS GPIO in 1588 function caps Anatoly Burakov
2024-06-12 15:00 ` [PATCH v2 065/148] net/ice/base: rename netlist check functions to match upstream Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 066/148] net/ice/base: fix check for existing switch rule Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 067/148] net/ice/base: fall back to safe CGU params Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 068/148] net/ice/base: change tmr_idx to u32 Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 069/148] net/ice/base: be more verbose when preparing timer sync Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 070/148] net/ice/base: be more verbose in configuring Rx timestamp offset Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 071/148] net/ice/base: match code style to upstream Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 072/148] net/ice/base: update strict status when assigning BW limits Anatoly Burakov
2024-06-20 13:32 ` Bruce Richardson
2024-06-12 15:01 ` [PATCH v2 073/148] net/ice/base: remove unused define Anatoly Burakov
2024-06-20 13:38 ` Bruce Richardson
2024-06-12 15:01 ` [PATCH v2 074/148] net/ice/base: improve read retry value calculation Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 075/148] net/ice/base: check if recipe buffer was already allocated Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 076/148] net/ice/base: fix handling recipes when reusing is not supported Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 077/148] net/ice/base: use correct type Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 078/148] net/ice/base: read OROM in a loop Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 079/148] net/ice/base: ignore snprintf return value Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 080/148] net/ice/base: check array bounds Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 081/148] net/ice/base: copy output IO params from command descriptor Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 082/148] net/ice/base: enable Next Cluster ID capability Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 083/148] net/ice/base: fix potential TLV length overflow Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 084/148] net/ice/base: add function to read SDP section from NVM Anatoly Burakov
2024-06-20 14:44 ` Bruce Richardson
2024-06-12 15:01 ` [PATCH v2 085/148] net/ice/base: add Floating VEB support Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 086/148] net/ice/base: add defines for loopback mode Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 087/148] net/ice/base: allow skipping PF clear Anatoly Burakov
2024-06-20 14:56 ` Bruce Richardson
2024-06-12 15:01 ` [PATCH v2 088/148] net/ice/base: fix in the definition of the Board Type Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 089/148] net/ice/base : make ice_clear_vsi_q_ctx() non-static Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 090/148] net/ice/base: fix package download algorithm Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 091/148] net/ice/base: allows packages with mixed signature presence Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 092/148] net/ice/base: fix ice_memcpy type specifiers Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 093/148] net/ice/base: allow different FW API versions based on MAC type Anatoly Burakov
2024-06-20 15:41 ` Bruce Richardson
2024-06-12 15:01 ` [PATCH v2 094/148] net/ice/base: add 32 GT bus speed enumerated value Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 095/148] net/ice/base: add E830 debug dump cluster ID values Anatoly Burakov
2024-06-20 15:43 ` Bruce Richardson
2024-06-12 15:01 ` [PATCH v2 096/148] net/ice/base: fix for preparing PHY for timesync command Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 097/148] net/ice/base: support for firmware sanitization Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 098/148] net/ice/base: add 200G speeds to PHY types decoding Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 099/148] net/ice/base: temporary workaround for E830 signed package support Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 100/148] net/ice/base: add PHY OFFSET_READY register clearing Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 101/148] net/ice/base: rename PHY model designator fields and functions Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 102/148] net/ice/base: enable SB access explicitly before 1st PHY access Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 103/148] net/ice/base: refactor ETH56G PHY initialization Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 104/148] net/ice/base: refactor ETH56G support for miltiple PHYs per MAC Anatoly Burakov
2024-06-18 16:19 ` Bruce Richardson
2024-06-12 15:01 ` [PATCH v2 105/148] net/ice/base: implement interface to reset timestamp memory Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 106/148] net/ice/base: fix iterations over PTP ports Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 107/148] net/ice/base: return high address for multi-read eth56g registers Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 108/148] net/ice/base: add function to read Tx timestamp status register Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 109/148] net/ice/base: implement upper-level PHY control functions Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 110/148] net/ice/base: squash multiple fixes for e56g device Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 111/148] net/ice/base: add PHY statistics dump Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 112/148] net/ice/base: move ice_ptp_init_phy_model to align with upstream Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 113/148] net/ice/base: add Get Link Status Data version 2 Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 114/148] net/ice/base: add port option commands Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 115/148] net/ice/base: merge unified E830 headers Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 116/148] net/ice/base: replace array initialization with macros Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 117/148] net/ice/base: switch speed conversions to static lookups Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 118/148] net/ice/base: support E830 in DDP pkg handling Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 119/148] net/ice/base: support E830 in Topology AQ command Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 120/148] net/ice/base: add E830 PTP init Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 121/148] net/ice/base: allow skipping main timer programming Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 122/148] net/ice/base: add missing files for shared code update Anatoly Burakov
2024-06-21 13:47 ` Bruce Richardson
2024-06-12 15:01 ` [PATCH v2 123/148] net/ice/base: align code to upstream Anatoly Burakov
2024-06-12 15:01 ` [PATCH v2 124/148] net/ice/base: use const char* array for storing link modes Anatoly Burakov
2024-06-21 14:00 ` Bruce Richardson
2024-06-12 15:01 ` [PATCH v2 125/148] net/ice/base: fix compile issues on some targets Anatoly Burakov
2024-06-18 17:05 ` Bruce Richardson
2024-06-12 15:02 ` [PATCH v2 126/148] net/ice/base: move code to common headers Anatoly Burakov
2024-06-21 14:02 ` Bruce Richardson
2024-06-12 15:02 ` [PATCH v2 127/148] net/ice/base: make some switch-related functions static Anatoly Burakov
2024-06-21 14:03 ` Bruce Richardson
2024-06-12 15:02 ` [PATCH v2 128/148] net/ice/base: add support for L2TP on switch Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 129/148] net/ice/base: add L2TPv3 support for adv rules Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 130/148] net/ice/base: detect and store device sensor reading capability Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 131/148] net/ice/base: add missing defines and misc cleanup Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 132/148] net/ice/base: increase PF reset wait timeout to 500 milliseconds Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 133/148] net/ice/base: fix memcpy type Anatoly Burakov
2024-06-21 14:40 ` Bruce Richardson
2024-06-12 15:02 ` [PATCH v2 134/148] net/ice/base: too big a timeout for QV diagnostic tests Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 135/148] net/ice/base: fix ice_get_ctx() issue Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 136/148] net/ice/base: add AQ function to configure SyncE error reporting Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 137/148] net/ice/base: support DCF query port ETS adminq Anatoly Burakov
2024-06-21 14:49 ` Bruce Richardson
2024-06-12 15:02 ` [PATCH v2 138/148] net/ice/base: update boost struct for traffic types Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 139/148] net/ice/base: clean up ice_lan_tx_rx Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 140/148] net/ice/base: enable CGU error reporting Anatoly Burakov
2024-06-21 15:08 ` Bruce Richardson
2024-06-12 15:02 ` [PATCH v2 141/148] net/ice/base: cleanup timestamp registers correctly Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 142/148] net/ice/base: rework multiple functions Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 143/148] net/ice/base: change a method to get pca9575 handle Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 144/148] net/ice/base: rename SMA register macros to match Linux upstream Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 145/148] net/ice/base: introduce new functions in ice_sched_node Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 146/148] net/ice/base: misc header file clean up Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 147/148] net/ice: update rss lut value for RSS init Anatoly Burakov
2024-06-12 15:02 ` [PATCH v2 148/148] net/ice: add new device ids Anatoly Burakov
2024-06-12 15:08 ` [PATCH v2 000/148] Update net/ice base driver to latest upstream snapshot Burakov, Anatoly
2024-06-12 15:51 ` Ferruh Yigit
2024-06-12 18:29 ` Burakov, Anatoly
2024-06-25 11:12 ` [PATCH v3 000/129] " Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 001/129] net/ice/base: convert enum ice_status to int Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 002/129] net/ice/base: replace ICE_SUCCESS with int Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 003/129] net/ice/base: add E830 definitions Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 004/129] net/ice/base: update phy config during link restart Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 005/129] net/ice/base: fix for pointer to variable outside scope Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 006/129] net/ice/base: add missing include Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 007/129] net/ice/base: add ability to set markid via switch filter Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 008/129] net/ice/base: improve ice_debug_cq messages Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 009/129] net/ice/base: add mgmt netlist auth support command Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 010/129] net/ice/base: avoid undefined variables Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 011/129] net/ice/base: improve media type handling for phy caps Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 012/129] net/ice/base: update flow seg fields to declared bitmaps Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 013/129] net/ice/base: update interface in ice_parse_common_caps Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 014/129] net/ice/base: refactor (non) bitmap declarations Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 015/129] net/ice/base: remove unnecessary control queue cmd_buf arrays Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 016/129] net/ice/base: alloc port_info only once Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 017/129] net/ice/base: update code with flex array safe allocations Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 018/129] net/ice/base: support for OROM update in recovery mode Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 019/129] net/ice/base: improve find recipe routine Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 020/129] net/ice/base: fix memory leak when checking firmware version Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 021/129] net/ice/base: add LL Tx timestamp interrupt read Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 022/129] net/ice/base: use model-dependent number of PHY ports Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 023/129] net/ice/base: use ice_bitmap_t in promisc functions Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 024/129] net/ice/base: fix rx-only unicast promiscuous mode Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 025/129] net/ice/base: add support for E825-C TX clock changing Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 026/129] net/ice/base: fix for applying multiple cloud filters Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 027/129] net/ice/base: prevent potential integer overflow Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 028/129] net/ice/base: implement initial PTP support for E830 Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 029/129] net/ice/base: fix resource leak Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 030/129] net/ice/base: move lock outside of if-else Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 031/129] net/ice/base: refactor control queue send delay Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 032/129] net/ice/base: allow for dumping all clusters Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 033/129] net/ice/base: remove PTP aqc_driver_params Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 034/129] net/ice/base: change data buffer in i2c write to be const Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 035/129] net/ice/base: fix sign-extension Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 036/129] net/ice/base: add helper function for refsync Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 037/129] net/ice/base: added informational message for NAC topology Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 038/129] net/ice/base: add Cage Max Power override NVM module Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 039/129] net/ice/base: adapt No FEC in Auto support check to add E82X devices Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 040/129] net/ice/base: fix incorrect size when allocating children arrays Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 041/129] net/ice/base: fix GCS descriptor field offsets Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 042/129] net/ice/base: add VSI type for subfunctions Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 043/129] net/ice/base: correct the return type of ice_bitmap_hweight Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 044/129] net/ice/base: fix ice_ptp_one_port_cmd to avoid stale PHY commands Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 045/129] net/ice/base: remove dead code from ice_get_ddp_pkg_state Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 046/129] net/ice/base: use ICE_PTP_NOP to better indicate no action Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 047/129] net/ice/base: add fw log file Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 048/129] net/ice/base: use "err" instead of "status" in ice_ptp_hw.c Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 049/129] net/ice/base: re-number E810-T subdevice IDs to match upstream Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 050/129] net/ice/base: enable RDMA Act-Act unload paths Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 051/129] net/ice/base: parse 1PPS GPIO in 1588 function caps Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 052/129] net/ice/base: fix check for existing switch rule Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 053/129] net/ice/base: fall back to safe CGU params Anatoly Burakov
2024-06-25 11:12 ` [PATCH v3 054/129] net/ice/base: change tmr_idx to u32 Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 055/129] net/ice/base: be more verbose when preparing timer sync Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 056/129] net/ice/base: update strict status when assigning BW limits Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 057/129] net/ice/base: improve read retry value calculation Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 058/129] net/ice/base: check if recipe buffer was already allocated Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 059/129] net/ice/base: use correct type Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 060/129] net/ice/base: read OROM in a loop Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 061/129] net/ice/base: ignore snprintf return value Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 062/129] net/ice/base: check array bounds Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 063/129] net/ice/base: copy output IO params from command descriptor Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 064/129] net/ice/base: enable Next Cluster ID capability Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 065/129] net/ice/base: fix potential TLV length overflow Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 066/129] net/ice/base: add function to read SDP section from NVM Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 067/129] net/ice/base: add Floating VEB support Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 068/129] net/ice/base: add defines for loopback mode Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 069/129] net/ice/base: allow skipping PF clear Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 070/129] net/ice/base: fix in the definition of the Board Type Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 071/129] net/ice/base: make ice_clear_vsi_q_ctx() non-static Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 072/129] net/ice/base: fix package download algorithm Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 073/129] net/ice/base: allows packages with mixed signature presence Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 074/129] net/ice/base: fix ice_memcpy type specifiers Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 075/129] net/ice/base: allow different FW API versions based on MAC type Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 076/129] net/ice/base: add 32 GT bus speed enumerated value Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 077/129] net/ice/base: add E830 debug dump cluster ID values Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 078/129] net/ice/base: fix for preparing PHY for timesync command Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 079/129] net/ice/base: support for firmware sanitization Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 080/129] net/ice/base: add 200G speeds to PHY types decoding Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 081/129] net/ice/base: add PHY OFFSET_READY register clearing Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 082/129] net/ice/base: rename PHY model designator fields and functions Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 083/129] net/ice/base: enable SB access explicitly before 1st PHY access Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 084/129] net/ice/base: refactor ETH56G PHY initialization Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 085/129] net/ice/base: refactor ETH56G support for multiple PHYs per MAC Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 086/129] net/ice/base: implement interface to reset timestamp memory Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 087/129] net/ice/base: return high address for multi-read eth56g registers Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 088/129] net/ice/base: add function to read Tx timestamp status register Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 089/129] net/ice/base: implement upper-level PHY control functions Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 090/129] net/ice/base: squash multiple fixes for e56g device Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 091/129] net/ice/base: allow passing flags to sbq command Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 092/129] net/ice/base: move ice_ptp_init_phy_model to align with upstream Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 093/129] net/ice/base: add Get Link Status Data version 2 Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 094/129] net/ice/base: add port option commands Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 095/129] net/ice/base: merge unified E830 headers Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 096/129] net/ice/base: replace array initialization with macros Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 097/129] net/ice/base: switch speed conversions to static lookups Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 098/129] net/ice/base: support E830 in DDP pkg handling Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 099/129] net/ice/base: support E830 in Topology AQ command Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 100/129] net/ice/base: add E830 PTP init Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 101/129] net/ice/base: allow skipping main timer programming Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 102/129] net/ice/base: add missing files for shared code update Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 103/129] net/ice/base: rename netlist check functions to match upstream Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 104/129] net/ice/base: align code to base driver Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 105/129] net/ice/base: use const char* array for storing link modes Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 106/129] net/ice/base: fix compile issues on some targets Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 107/129] net/ice/base: move code to common headers Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 108/129] net/ice/base: make some switch-related functions static Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 109/129] net/ice/base: add L2TPv3 support for adv rules Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 110/129] net/ice/base: detect and store device sensor reading capability Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 111/129] net/ice/base: add missing defines and misc cleanup Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 112/129] net/ice/base: increase PF reset wait timeout to 500 milliseconds Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 113/129] net/ice/base: adjust memcpy type Anatoly Burakov
2024-06-25 11:13 ` [PATCH v3 114/129] net/ice/base: use a variable to store reset count Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 115/129] net/ice/base: fix ice_get_ctx() issue Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 116/129] net/ice/base: add AQ function to configure SyncE error reporting Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 117/129] net/ice/base: support DCF query port ETS adminq Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 118/129] net/ice/base: update boost struct for traffic types Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 119/129] net/ice/base: clean up ice_lan_tx_rx Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 120/129] net/ice/base: enable CGU error reporting Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 121/129] net/ice/base: cleanup timestamp registers correctly Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 122/129] net/ice/base: remove PHY port timer bypass mode Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 123/129] net/ice/base: implement TX interrupt enablement functions Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 124/129] net/ice/base: make Tx and Rx vernier offset calibration independent Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 125/129] net/ice/base: change a method to get pca9575 handle Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 126/129] net/ice/base: rename SMA register macros to match Linux upstream Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 127/129] net/ice/base: introduce new functions in ice_sched_node Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 128/129] net/ice/base: misc header file clean up Anatoly Burakov
2024-06-25 11:14 ` [PATCH v3 129/129] net/ice: add new device ids Anatoly Burakov
2024-06-25 17:20 ` [PATCH v3 000/129] Update net/ice base driver to latest upstream snapshot Bruce Richardson
2024-06-26 11:40 ` [PATCH v4 000/103] " Anatoly Burakov
2024-06-26 11:40 ` [PATCH v4 001/103] net/ice/base: add LL Tx timestamp interrupt read Anatoly Burakov
2024-06-26 11:40 ` [PATCH v4 002/103] net/ice/base: use model-dependent number of PHY ports Anatoly Burakov
2024-06-26 11:40 ` [PATCH v4 003/103] net/ice/base: use ice_bitmap_t in promisc functions Anatoly Burakov
2024-06-26 11:40 ` [PATCH v4 004/103] net/ice/base: fix rx-only unicast promiscuous mode Anatoly Burakov
2024-06-26 11:40 ` [PATCH v4 005/103] net/ice/base: add support for E825-C TX clock changing Anatoly Burakov
2024-06-26 11:40 ` [PATCH v4 006/103] net/ice/base: fix for applying multiple cloud filters Anatoly Burakov
2024-06-26 11:40 ` [PATCH v4 007/103] net/ice/base: prevent potential integer overflow Anatoly Burakov
2024-06-26 11:40 ` [PATCH v4 008/103] net/ice/base: implement initial PTP support for E830 Anatoly Burakov
2024-06-26 11:40 ` [PATCH v4 009/103] net/ice/base: fix resource leak Anatoly Burakov
2024-06-26 11:40 ` [PATCH v4 010/103] net/ice/base: move lock outside of if-else Anatoly Burakov
2024-06-26 11:40 ` [PATCH v4 011/103] net/ice/base: refactor control queue send delay Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 012/103] net/ice/base: allow for dumping all clusters Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 013/103] net/ice/base: remove PTP aqc_driver_params Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 014/103] net/ice/base: change data buffer in i2c write to be const Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 015/103] net/ice/base: fix sign-extension Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 016/103] net/ice/base: add helper function for refsync Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 017/103] net/ice/base: added informational message for NAC topology Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 018/103] net/ice/base: add Cage Max Power override NVM module Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 019/103] net/ice/base: adapt No FEC in Auto support check to add E82X devices Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 020/103] net/ice/base: fix incorrect size when allocating children arrays Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 021/103] net/ice/base: fix GCS descriptor field offsets Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 022/103] net/ice/base: add VSI type for subfunctions Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 023/103] net/ice/base: correct the return type of ice_bitmap_hweight Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 024/103] net/ice/base: add helper to get timer command reg values Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 025/103] net/ice/base: avoid stale PHY commands in ice_ptp_one_port_cmd Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 026/103] net/ice/base: remove dead code from ice_get_ddp_pkg_state Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 027/103] net/ice/base: use ICE_PTP_NOP to better indicate no action Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 028/103] net/ice/base: use "err" instead of "status" in ice_ptp_hw.c Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 029/103] net/ice/base: re-number E810-T subdevice IDs to match upstream Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 030/103] net/ice/base: enable RDMA Act-Act unload paths Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 031/103] net/ice/base: parse 1PPS GPIO in 1588 function caps Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 032/103] net/ice/base: fix check for existing switch rule Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 033/103] net/ice/base: fall back to safe CGU params Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 034/103] net/ice/base: change tmr_idx to u32 Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 035/103] net/ice/base: be more verbose when preparing timer sync Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 036/103] net/ice/base: update strict status when assigning BW limits Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 037/103] net/ice/base: improve read retry value calculation Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 038/103] net/ice/base: check if recipe buffer was already allocated Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 039/103] net/ice/base: use correct type Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 040/103] net/ice/base: read OROM in a loop Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 041/103] net/ice/base: ignore snprintf return value Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 042/103] net/ice/base: check array bounds Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 043/103] net/ice/base: copy output IO params from command descriptor Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 044/103] net/ice/base: enable Next Cluster ID capability Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 045/103] net/ice/base: fix potential TLV length overflow Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 046/103] net/ice/base: add function to read SDP section from NVM Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 047/103] net/ice/base: add Floating VEB support Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 048/103] net/ice/base: add defines for loopback mode Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 049/103] net/ice/base: allow skipping PF clear Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 050/103] net/ice/base: fix wrong definition of board type Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 051/103] net/ice/base: make ice_clear_vsi_q_ctx() non-static Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 052/103] net/ice/base: fix package download algorithm Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 053/103] net/ice/base: allows packages with mixed signature presence Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 054/103] net/ice/base: adjust ice_memcpy type specifiers Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 055/103] net/ice/base: allow different FW API versions based on MAC type Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 056/103] net/ice/base: add 32 GT bus speed enumerated value Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 057/103] net/ice/base: add E830 debug dump cluster ID values Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 058/103] net/ice/base: fix for preparing PHY for timesync command Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 059/103] net/ice/base: support for firmware sanitization Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 060/103] net/ice/base: add 200G speeds to PHY types decoding Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 061/103] net/ice/base: add PHY OFFSET_READY register clearing Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 062/103] net/ice/base: rename PHY model designator fields and functions Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 063/103] net/ice/base: enable SB access explicitly before 1st PHY access Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 064/103] net/ice/base: refactor ETH56G PHY initialization Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 065/103] net/ice/base: refactor ETH56G support for multiple PHYs per MAC Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 066/103] net/ice/base: implement interface to reset timestamp memory Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 067/103] net/ice/base: return high address for multi-read eth56g registers Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 068/103] net/ice/base: add function to read Tx timestamp status register Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 069/103] net/ice/base: implement upper-level PHY control functions Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 070/103] net/ice/base: remove switch-related code Anatoly Burakov
2024-06-26 11:41 ` [PATCH v4 071/103] net/ice/base: allow passing flags to sbq command Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 072/103] net/ice/base: add Get Link Status Data version 2 Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 073/103] net/ice/base: add port option commands Anatoly Burakov
2024-06-26 12:13 ` Burakov, Anatoly
2024-06-26 11:42 ` [PATCH v4 074/103] net/ice/base: replace array initialization with macros Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 075/103] net/ice/base: switch speed conversions to static lookups Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 076/103] net/ice/base: merge unified E830 headers Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 077/103] net/ice/base: support E830 in DDP pkg handling Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 078/103] net/ice/base: support E830 in Topology AQ command Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 079/103] net/ice/base: add E830 PTP init Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 080/103] net/ice/base: allow skipping main timer programming Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 081/103] net/ice/base: fix compile issues on some targets Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 082/103] net/ice/base: add L2TPv3 support for adv rules Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 083/103] net/ice/base: detect and store device sensor reading capability Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 084/103] net/ice/base: increase PF reset wait timeout to 500 milliseconds Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 085/103] net/ice/base: use a variable to store reset count Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 086/103] net/ice/base: fix masking in ice_get_ctx() Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 087/103] net/ice/base: add AQ function to configure SyncE error reporting Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 088/103] net/ice/base: update boost struct for traffic types Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 089/103] net/ice/base: enable CGU error reporting Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 090/103] net/ice/base: cleanup timestamp registers correctly Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 091/103] net/ice/base: remove PHY port timer bypass mode Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 092/103] net/ice/base: implement TX interrupt enablement functions Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 093/103] net/ice/base: make Tx and Rx vernier offset calibration independent Anatoly Burakov
2024-06-26 12:11 ` Burakov, Anatoly
2024-06-26 12:13 ` Bruce Richardson
2024-06-26 11:42 ` [PATCH v4 094/103] net/ice/base: change a method to get pca9575 handle Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 095/103] net/ice/base: rename SMA register macros Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 096/103] net/ice/base: make is_gps_present more generic Anatoly Burakov
2024-06-26 12:08 ` Burakov, Anatoly
2024-06-26 11:42 ` [PATCH v4 097/103] net/ice/base: add missing defines and misc cleanup Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 098/103] net/ice/base: align code to base driver Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 099/103] net/ice/base: make some functions non-static Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 100/103] net/ice/base: make some functions static Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 101/103] net/ice/base: introduce new functions in ice_sched_node Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 102/103] net/ice/base: add missing files for shared code update Anatoly Burakov
2024-06-26 11:42 ` [PATCH v4 103/103] net/ice: add new device ids Anatoly Burakov
2024-06-26 17:33 ` [PATCH v4 000/103] Update net/ice base driver to latest upstream snapshot Bruce Richardson
2024-06-27 17:43 ` Bruce Richardson
2024-06-28 11:23 ` Bruce Richardson
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