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From: Tyler Retzlaff <roretzla@linux.microsoft.com>
To: dev@dpdk.org
Cc: Ajit Khaparde <ajit.khaparde@broadcom.com>,
Andrew Boyer <andrew.boyer@amd.com>,
Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>,
Bruce Richardson <bruce.richardson@intel.com>,
Chenbo Xia <chenbox@nvidia.com>, Chengwen Feng <fengchengwen@huawei.com>,
Dariusz Sosnowski <dsosnowski@nvidia.com>,
David Christensen <drc@linux.vnet.ibm.com>,
Hyong Youb Kim <hyonkim@cisco.com>, Jerin Jacob <jerinj@marvell.com>,
Jie Hai <haijie1@huawei.com>, Jingjing Wu <jingjing.wu@intel.com>,
John Daley <johndale@cisco.com>, Kevin Laatz <kevin.laatz@intel.com>,
Kiran Kumar K <kirankumark@marvell.com>,
Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>,
Maciej Czekaj <mczekaj@marvell.com>, Matan Azrad <matan@nvidia.com>,
Maxime Coquelin <maxime.coquelin@redhat.com>,
Nithin Dabilpuram <ndabilpuram@marvell.com>, Ori Kam <orika@nvidia.com>,
Ruifeng Wang <ruifeng.wang@arm.com>, Satha Rao <skoteshwar@marvell.com>,
Somnath Kotur <somnath.kotur@broadcom.com>,
Suanming Mou <suanmingm@nvidia.com>, Sunil Kumar Kori <skori@marvell.com>,
Viacheslav Ovsiienko <viacheslavo@nvidia.com>,
Yisen Zhuang <yisen.zhuang@huawei.com>,
Yuying Zhang <Yuying.Zhang@intel.com>, mb@smartsharesystems.com,
Tyler Retzlaff <roretzla@linux.microsoft.com>
Subject: [PATCH v5 07/22] common/idpf: use mbuf descriptor accessors
Date: Sat, 24 Feb 2024 00:21:52 -0800
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RTE_MARKER typedefs are a GCC extension unsupported by MSVC. Use
new rte_mbuf_rearm_data and rte_mbuf_rx_descriptor_fields1 accessors
that provide a compatible type pointer without using the marker fields.
Signed-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>
---
drivers/common/idpf/idpf_common_rxtx.c | 4 +---
drivers/common/idpf/idpf_common_rxtx_avx512.c | 33 ++++++++++++++-------------
2 files changed, 18 insertions(+), 19 deletions(-)
diff --git a/drivers/common/idpf/idpf_common_rxtx.c b/drivers/common/idpf/idpf_common_rxtx.c
index 83b131e..62ddf2e 100644
--- a/drivers/common/idpf/idpf_common_rxtx.c
+++ b/drivers/common/idpf/idpf_common_rxtx.c
@@ -1595,7 +1595,6 @@
static inline int
idpf_rxq_vec_setup_default(struct idpf_rx_queue *rxq)
{
- uintptr_t p;
struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
mb_def.nb_segs = 1;
@@ -1605,8 +1604,7 @@
/* prevent compiler reordering: rearm_data covers previous fields */
rte_compiler_barrier();
- p = (uintptr_t)&mb_def.rearm_data;
- rxq->mbuf_initializer = *(uint64_t *)p;
+ rxq->mbuf_initializer = *rte_mbuf_rearm_data(&mb_def);
return 0;
}
diff --git a/drivers/common/idpf/idpf_common_rxtx_avx512.c b/drivers/common/idpf/idpf_common_rxtx_avx512.c
index f65e8d5..f978a27 100644
--- a/drivers/common/idpf/idpf_common_rxtx_avx512.c
+++ b/drivers/common/idpf/idpf_common_rxtx_avx512.c
@@ -462,6 +462,7 @@
RTE_ALIGN(offsetof(struct rte_mbuf,
rearm_data),
16));
+
/* build up data and do writes */
__m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
rearm6, rearm7;
@@ -476,13 +477,13 @@
rearm0 = _mm256_permute2f128_si256(mbuf_init, mb0_1, 0x20);
/* write to mbuf */
- _mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
+ _mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 6]),
rearm6);
- _mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
+ _mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 4]),
rearm4);
- _mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
+ _mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 2]),
rearm2);
- _mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
+ _mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 0]),
rearm0);
rearm7 = _mm256_blend_epi32(mbuf_init, mb6_7, 0xF0);
@@ -491,13 +492,13 @@
rearm1 = _mm256_blend_epi32(mbuf_init, mb0_1, 0xF0);
/* again write to mbufs */
- _mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
+ _mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 7]),
rearm7);
- _mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
+ _mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 5]),
rearm5);
- _mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
+ _mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 3]),
rearm3);
- _mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
+ _mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 1]),
rearm1);
/* perform dd_check */
@@ -936,13 +937,13 @@
rearm0 = _mm256_permute2f128_si256(mbuf_init, mb0_1, 0x20);
/* write to mbuf */
- _mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
+ _mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 6]),
rearm6);
- _mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
+ _mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 4]),
rearm4);
- _mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
+ _mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 2]),
rearm2);
- _mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
+ _mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 0]),
rearm0);
rearm7 = _mm256_blend_epi32(mbuf_init, mb6_7, 0xF0);
@@ -951,13 +952,13 @@
rearm1 = _mm256_blend_epi32(mbuf_init, mb0_1, 0xF0);
/* again write to mbufs */
- _mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
+ _mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 7]),
rearm7);
- _mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
+ _mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 5]),
rearm5);
- _mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
+ _mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 3]),
rearm3);
- _mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
+ _mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 1]),
rearm1);
const __mmask8 dd_mask = _mm512_cmpeq_epi64_mask(
--
1.8.3.1