From mboxrd@z Thu Jan 1 00:00:00 1970
Return-Path: <dev-bounces@dpdk.org>
Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124])
by inbox.dpdk.org (Postfix) with ESMTP id B798F43E7E;
Mon, 15 Apr 2024 22:12:30 +0200 (CEST)
Received: from mails.dpdk.org (localhost [127.0.0.1])
by mails.dpdk.org (Postfix) with ESMTP id 2DCB842E18;
Mon, 15 Apr 2024 22:06:23 +0200 (CEST)
Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182])
by mails.dpdk.org (Postfix) with ESMTP id 0146540DF5
for <dev@dpdk.org>; Mon, 15 Apr 2024 22:05:05 +0200 (CEST)
Received: by linux.microsoft.com (Postfix, from userid 1086)
id 41A4B20FD8D1; Mon, 15 Apr 2024 13:04:47 -0700 (PDT)
DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 41A4B20FD8D1
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;
s=default; t=1713211491;
bh=jU/wciiNLTJm2GMuUcH80RvErDNkqyBOJNALLx6Zxvc=;
h=From:To:Cc:Subject:Date:In-Reply-To:References:From;
b=Y7mcpZLd7v/rlEgQfgL3ZzR3UQr0Jn68qIuFeyvgEjSGfirGCS2s4G2ORrtGE+wmq
SCJLpiJ0h8Q5+w8VHEVC6QU4p+/46c+9TsUTFw898fqiWNIk1kaEg+OH4vl26JIfb6
C954xrhdlslzZioDWZb/0ANx0LyakmIq+/pz9quA=
From: Tyler Retzlaff <roretzla@linux.microsoft.com>
To: dev@dpdk.org
Cc: =?UTF-8?q?Mattias=20R=C3=B6nnblom?= <mattias.ronnblom@ericsson.com>,
"Min Hu (Connor)" <humin29@huawei.com>,
=?UTF-8?q?Morten=20Br=C3=B8rup?= <mb@smartsharesystems.com>,
Abdullah Sevincer <abdullah.sevincer@intel.com>,
Ajit Khaparde <ajit.khaparde@broadcom.com>,
Akhil Goyal <gakhil@marvell.com>, Alok Prasad <palok@marvell.com>,
Amit Bernstein <amitbern@amazon.com>,
Anatoly Burakov <anatoly.burakov@intel.com>,
Andrew Boyer <andrew.boyer@amd.com>,
Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>,
Ankur Dwivedi <adwivedi@marvell.com>, Anoob Joseph <anoobj@marvell.com>,
Ashish Gupta <ashish.gupta@marvell.com>,
Ashwin Sekhar T K <asekhar@marvell.com>,
Bruce Richardson <bruce.richardson@intel.com>,
Byron Marohn <byron.marohn@intel.com>,
Chaoyong He <chaoyong.he@corigine.com>, Chas Williams <chas3@att.com>,
Chenbo Xia <chenbox@nvidia.com>, Chengwen Feng <fengchengwen@huawei.com>,
Conor Walsh <conor.walsh@intel.com>,
Cristian Dumitrescu <cristian.dumitrescu@intel.com>,
Dariusz Sosnowski <dsosnowski@nvidia.com>,
David Hunt <david.hunt@intel.com>,
Devendra Singh Rawat <dsinghrawat@marvell.com>,
Ed Czeck <ed.czeck@atomicrules.com>,
Evgeny Schemeilin <evgenys@amazon.com>, Fan Zhang <fanzhang.oss@gmail.com>,
Gagandeep Singh <g.singh@nxp.com>, Guoyang Zhou <zhouguoyang@huawei.com>,
Harman Kalra <hkalra@marvell.com>,
Harry van Haaren <harry.van.haaren@intel.com>,
Hemant Agrawal <hemant.agrawal@nxp.com>,
Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>,
Hyong Youb Kim <hyonkim@cisco.com>, Jakub Grajciar <jgrajcia@cisco.com>,
Jerin Jacob <jerinj@marvell.com>, Jian Wang <jianwang@trustnetic.com>,
Jiawen Wu <jiawenwu@trustnetic.com>, Jie Hai <haijie1@huawei.com>,
Jingjing Wu <jingjing.wu@intel.com>, John Daley <johndale@cisco.com>,
John Miller <john.miller@atomicrules.com>, Joyce Kong <joyce.kong@arm.com>,
Kai Ji <kai.ji@intel.com>, Kevin Laatz <kevin.laatz@intel.com>,
Kiran Kumar K <kirankumark@marvell.com>,
Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>,
Lee Daly <lee.daly@intel.com>, Liang Ma <liangma@liangbit.com>,
Liron Himi <lironh@marvell.com>, Long Li <longli@microsoft.com>,
Maciej Czekaj <mczekaj@marvell.com>, Matan Azrad <matan@nvidia.com>,
Matt Peters <matt.peters@windriver.com>,
Maxime Coquelin <maxime.coquelin@redhat.com>,
Michael Shamis <michaelsh@marvell.com>,
Nagadheeraj Rottela <rnagadheeraj@marvell.com>,
Nicolas Chautru <nicolas.chautru@intel.com>,
Nithin Dabilpuram <ndabilpuram@marvell.com>, Ori Kam <orika@nvidia.com>,
Pablo de Lara <pablo.de.lara.guarch@intel.com>,
Pavan Nikhilesh <pbhagavatula@marvell.com>,
Peter Mccarthy <peter.mccarthy@intel.com>,
Radu Nicolau <radu.nicolau@intel.com>,
Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>,
Rakesh Kudurumalla <rkudurumalla@marvell.com>,
Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>,
Reshma Pattan <reshma.pattan@intel.com>, Ron Beider <rbeider@amazon.com>,
Ruifeng Wang <ruifeng.wang@arm.com>, Sachin Saxena <sachin.saxena@nxp.com>,
Selwin Sebastian <selwin.sebastian@amd.com>,
Shai Brandes <shaibran@amazon.com>,
Shepard Siegel <shepard.siegel@atomicrules.com>,
Shijith Thotton <sthotton@marvell.com>,
Sivaprasad Tummala <sivaprasad.tummala@amd.com>,
Somnath Kotur <somnath.kotur@broadcom.com>,
Srikanth Yalavarthi <syalavarthi@marvell.com>,
Stephen Hemminger <stephen@networkplumber.org>,
Steven Webster <steven.webster@windriver.com>,
Suanming Mou <suanmingm@nvidia.com>, Sunil Kumar Kori <skori@marvell.com>,
Sunil Uttarwar <sunilprakashrao.uttarwar@amd.com>,
Sunila Sahu <ssahu@marvell.com>, Tejasree Kondoj <ktejasree@marvell.com>,
Viacheslav Ovsiienko <viacheslavo@nvidia.com>,
Vikas Gupta <vikas.gupta@broadcom.com>,
Volodymyr Fialko <vfialko@marvell.com>,
Wajeeh Atrash <atrwajee@amazon.com>, Wisam Jaddo <wisamm@nvidia.com>,
Xiaoyun Wang <cloud.wangxiaoyun@huawei.com>,
Yipeng Wang <yipeng1.wang@intel.com>,
Yisen Zhuang <yisen.zhuang@huawei.com>,
Yuying Zhang <Yuying.Zhang@intel.com>,
Zhangfei Gao <zhangfei.gao@linaro.org>, Zhirun Yan <yanzhirun_163@163.com>,
Ziyang Xuan <xuanziyang2@huawei.com>,
Tyler Retzlaff <roretzla@linux.microsoft.com>
Subject: [PATCH v2 46/83] event/cnxk: move alignment attribute on types
Date: Mon, 15 Apr 2024 13:04:08 -0700
Message-Id: <1713211485-9021-47-git-send-email-roretzla@linux.microsoft.com>
X-Mailer: git-send-email 1.8.3.1
In-Reply-To: <1713211485-9021-1-git-send-email-roretzla@linux.microsoft.com>
References: <1710949096-5786-1-git-send-email-roretzla@linux.microsoft.com>
<1713211485-9021-1-git-send-email-roretzla@linux.microsoft.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/dev>,
<mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/dev>,
<mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
Move location of __rte_aligned(a) to new conventional location. The new
placement between {struct,union} and the tag allows the desired
alignment to be imparted on the type regardless of the toolchain being
used for both C and C++. Additionally, it avoids confusion by Doxygen
when generating documentation.
Signed-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>
Acked-by: Morten Brørup <mb@smartsharesystems.com>
---
drivers/event/cnxk/cn10k_eventdev.h | 8 ++++----
drivers/event/cnxk/cnxk_eventdev.h | 24 ++++++++++++------------
drivers/event/cnxk/cnxk_tim_evdev.h | 4 ++--
drivers/event/cnxk/cnxk_tim_worker.c | 2 +-
4 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/event/cnxk/cn10k_eventdev.h b/drivers/event/cnxk/cn10k_eventdev.h
index e79b68e..3721214 100644
--- a/drivers/event/cnxk/cn10k_eventdev.h
+++ b/drivers/event/cnxk/cn10k_eventdev.h
@@ -8,7 +8,7 @@
#define CN10K_SSO_DEFAULT_STASH_OFFSET -1
#define CN10K_SSO_DEFAULT_STASH_LENGTH 2
-struct cn10k_sso_hws {
+struct __rte_cache_aligned cn10k_sso_hws {
uint64_t base;
uint32_t gw_wdata;
void *lookup_mem;
@@ -19,15 +19,15 @@ struct cn10k_sso_hws {
struct cnxk_timesync_info **tstamp;
uint64_t meta_aura;
/* Add Work Fastpath data */
- int64_t *fc_mem __rte_cache_aligned;
+ alignas(RTE_CACHE_LINE_SIZE) int64_t *fc_mem;
int64_t *fc_cache_space;
uintptr_t aw_lmt;
uintptr_t grp_base;
int32_t xaq_lmt;
/* Tx Fastpath data */
- uintptr_t lmt_base __rte_cache_aligned;
+ alignas(RTE_CACHE_LINE_SIZE) uintptr_t lmt_base;
uint64_t lso_tun_fmt;
uint8_t tx_adptr_data[];
-} __rte_cache_aligned;
+};
#endif /* __CN10K_EVENTDEV_H__ */
diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h
index fa99ded..ece4939 100644
--- a/drivers/event/cnxk/cnxk_eventdev.h
+++ b/drivers/event/cnxk/cnxk_eventdev.h
@@ -80,7 +80,7 @@ struct cnxk_sso_stash {
uint16_t stash_length;
};
-struct cnxk_sso_evdev {
+struct __rte_cache_aligned cnxk_sso_evdev {
struct roc_sso sso;
uint8_t max_event_queues;
uint8_t max_event_ports;
@@ -124,10 +124,10 @@ struct cnxk_sso_evdev {
uint32_t gw_mode;
uint16_t stash_cnt;
struct cnxk_sso_stash *stash_parse_data;
-} __rte_cache_aligned;
+};
/* Event port a.k.a GWS */
-struct cn9k_sso_hws {
+struct __rte_cache_aligned cn9k_sso_hws {
uint64_t base;
uint64_t gw_wdata;
void *lookup_mem;
@@ -136,15 +136,15 @@ struct cn9k_sso_hws {
/* PTP timestamp */
struct cnxk_timesync_info **tstamp;
/* Add Work Fastpath data */
- uint64_t xaq_lmt __rte_cache_aligned;
+ alignas(RTE_CACHE_LINE_SIZE) uint64_t xaq_lmt;
uint64_t *fc_mem;
uintptr_t grp_base;
/* Tx Fastpath data */
- uint64_t lso_tun_fmt __rte_cache_aligned;
+ alignas(RTE_CACHE_LINE_SIZE) uint64_t lso_tun_fmt;
uint8_t tx_adptr_data[];
-} __rte_cache_aligned;
+};
-struct cn9k_sso_hws_dual {
+struct __rte_cache_aligned cn9k_sso_hws_dual {
uint64_t base[2]; /* Ping and Pong */
uint64_t gw_wdata;
void *lookup_mem;
@@ -154,18 +154,18 @@ struct cn9k_sso_hws_dual {
/* PTP timestamp */
struct cnxk_timesync_info **tstamp;
/* Add Work Fastpath data */
- uint64_t xaq_lmt __rte_cache_aligned;
+ alignas(RTE_CACHE_LINE_SIZE) uint64_t xaq_lmt;
uint64_t *fc_mem;
uintptr_t grp_base;
/* Tx Fastpath data */
- uint64_t lso_tun_fmt __rte_cache_aligned;
+ alignas(RTE_CACHE_LINE_SIZE) uint64_t lso_tun_fmt;
uint8_t tx_adptr_data[];
-} __rte_cache_aligned;
+};
-struct cnxk_sso_hws_cookie {
+struct __rte_cache_aligned cnxk_sso_hws_cookie {
const struct rte_eventdev *event_dev;
bool configured;
-} __rte_cache_aligned;
+};
static inline int
parse_kvargs_flag(const char *key, const char *value, void *opaque)
diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h
index b91fcb3..6cf10db 100644
--- a/drivers/event/cnxk/cnxk_tim_evdev.h
+++ b/drivers/event/cnxk/cnxk_tim_evdev.h
@@ -123,7 +123,7 @@ struct cnxk_tim_bkt {
uint64_t pad;
};
-struct cnxk_tim_ring {
+struct __rte_cache_aligned cnxk_tim_ring {
uint16_t nb_chunk_slots;
uint32_t nb_bkts;
uintptr_t tbase;
@@ -149,7 +149,7 @@ struct cnxk_tim_ring {
uint64_t nb_chunks;
uint64_t chunk_sz;
enum roc_tim_clk_src clk_src;
-} __rte_cache_aligned;
+};
struct cnxk_tim_ent {
uint64_t w0;
diff --git a/drivers/event/cnxk/cnxk_tim_worker.c b/drivers/event/cnxk/cnxk_tim_worker.c
index 944490d..1f2f2fe 100644
--- a/drivers/event/cnxk/cnxk_tim_worker.c
+++ b/drivers/event/cnxk/cnxk_tim_worker.c
@@ -92,7 +92,7 @@
const uint64_t timeout_tick,
const uint16_t nb_timers, const uint8_t flags)
{
- struct cnxk_tim_ent entry[CNXK_TIM_MAX_BURST] __rte_cache_aligned;
+ alignas(RTE_CACHE_LINE_SIZE) struct cnxk_tim_ent entry[CNXK_TIM_MAX_BURST];
struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv;
uint16_t set_timers = 0;
uint16_t arr_idx = 0;
--
1.8.3.1