From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: <dev-bounces@dpdk.org> Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 47AB743E7E; Mon, 15 Apr 2024 22:13:35 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CA0D642E54; Mon, 15 Apr 2024 22:06:39 +0200 (CEST) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id 1AAAE40E72 for <dev@dpdk.org>; Mon, 15 Apr 2024 22:05:08 +0200 (CEST) Received: by linux.microsoft.com (Postfix, from userid 1086) id 346C820FDAA9; Mon, 15 Apr 2024 13:04:47 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 346C820FDAA9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1713211492; bh=jriG8rCpL0l/QItrishA8K3UvtmHyKuK8I+xAgM2ePc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VhlPGmcsl8+3EacLM6gcengfcZtT+SlmCnSBVxuN0BArz2p7LsIoYPF/wvUM5i2Gq knsMIz6Chs5RQ9Yzh1YMAFXo8QPNQ3huAplSfodJ94VJ45sGBDgEWUoweWGcDfLHLq hkmukH+k5g1+AWjQnDPSrmWTF8fagQhsGUq7U5Z8= From: Tyler Retzlaff <roretzla@linux.microsoft.com> To: dev@dpdk.org Cc: =?UTF-8?q?Mattias=20R=C3=B6nnblom?= <mattias.ronnblom@ericsson.com>, "Min Hu (Connor)" <humin29@huawei.com>, =?UTF-8?q?Morten=20Br=C3=B8rup?= <mb@smartsharesystems.com>, Abdullah Sevincer <abdullah.sevincer@intel.com>, Ajit Khaparde <ajit.khaparde@broadcom.com>, Akhil Goyal <gakhil@marvell.com>, Alok Prasad <palok@marvell.com>, Amit Bernstein <amitbern@amazon.com>, Anatoly Burakov <anatoly.burakov@intel.com>, Andrew Boyer <andrew.boyer@amd.com>, Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>, Ankur Dwivedi <adwivedi@marvell.com>, Anoob Joseph <anoobj@marvell.com>, Ashish Gupta <ashish.gupta@marvell.com>, Ashwin Sekhar T K <asekhar@marvell.com>, Bruce Richardson <bruce.richardson@intel.com>, Byron Marohn <byron.marohn@intel.com>, Chaoyong He <chaoyong.he@corigine.com>, Chas Williams <chas3@att.com>, Chenbo Xia <chenbox@nvidia.com>, Chengwen Feng <fengchengwen@huawei.com>, Conor Walsh <conor.walsh@intel.com>, Cristian Dumitrescu <cristian.dumitrescu@intel.com>, Dariusz Sosnowski <dsosnowski@nvidia.com>, David Hunt <david.hunt@intel.com>, Devendra Singh Rawat <dsinghrawat@marvell.com>, Ed Czeck <ed.czeck@atomicrules.com>, Evgeny Schemeilin <evgenys@amazon.com>, Fan Zhang <fanzhang.oss@gmail.com>, Gagandeep Singh <g.singh@nxp.com>, Guoyang Zhou <zhouguoyang@huawei.com>, Harman Kalra <hkalra@marvell.com>, Harry van Haaren <harry.van.haaren@intel.com>, Hemant Agrawal <hemant.agrawal@nxp.com>, Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>, Hyong Youb Kim <hyonkim@cisco.com>, Jakub Grajciar <jgrajcia@cisco.com>, Jerin Jacob <jerinj@marvell.com>, Jian Wang <jianwang@trustnetic.com>, Jiawen Wu <jiawenwu@trustnetic.com>, Jie Hai <haijie1@huawei.com>, Jingjing Wu <jingjing.wu@intel.com>, John Daley <johndale@cisco.com>, John Miller <john.miller@atomicrules.com>, Joyce Kong <joyce.kong@arm.com>, Kai Ji <kai.ji@intel.com>, Kevin Laatz <kevin.laatz@intel.com>, Kiran Kumar K <kirankumark@marvell.com>, Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>, Lee Daly <lee.daly@intel.com>, Liang Ma <liangma@liangbit.com>, Liron Himi <lironh@marvell.com>, Long Li <longli@microsoft.com>, Maciej Czekaj <mczekaj@marvell.com>, Matan Azrad <matan@nvidia.com>, Matt Peters <matt.peters@windriver.com>, Maxime Coquelin <maxime.coquelin@redhat.com>, Michael Shamis <michaelsh@marvell.com>, Nagadheeraj Rottela <rnagadheeraj@marvell.com>, Nicolas Chautru <nicolas.chautru@intel.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, Ori Kam <orika@nvidia.com>, Pablo de Lara <pablo.de.lara.guarch@intel.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, Peter Mccarthy <peter.mccarthy@intel.com>, Radu Nicolau <radu.nicolau@intel.com>, Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>, Rakesh Kudurumalla <rkudurumalla@marvell.com>, Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>, Reshma Pattan <reshma.pattan@intel.com>, Ron Beider <rbeider@amazon.com>, Ruifeng Wang <ruifeng.wang@arm.com>, Sachin Saxena <sachin.saxena@nxp.com>, Selwin Sebastian <selwin.sebastian@amd.com>, Shai Brandes <shaibran@amazon.com>, Shepard Siegel <shepard.siegel@atomicrules.com>, Shijith Thotton <sthotton@marvell.com>, Sivaprasad Tummala <sivaprasad.tummala@amd.com>, Somnath Kotur <somnath.kotur@broadcom.com>, Srikanth Yalavarthi <syalavarthi@marvell.com>, Stephen Hemminger <stephen@networkplumber.org>, Steven Webster <steven.webster@windriver.com>, Suanming Mou <suanmingm@nvidia.com>, Sunil Kumar Kori <skori@marvell.com>, Sunil Uttarwar <sunilprakashrao.uttarwar@amd.com>, Sunila Sahu <ssahu@marvell.com>, Tejasree Kondoj <ktejasree@marvell.com>, Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Vikas Gupta <vikas.gupta@broadcom.com>, Volodymyr Fialko <vfialko@marvell.com>, Wajeeh Atrash <atrwajee@amazon.com>, Wisam Jaddo <wisamm@nvidia.com>, Xiaoyun Wang <cloud.wangxiaoyun@huawei.com>, Yipeng Wang <yipeng1.wang@intel.com>, Yisen Zhuang <yisen.zhuang@huawei.com>, Yuying Zhang <Yuying.Zhang@intel.com>, Zhangfei Gao <zhangfei.gao@linaro.org>, Zhirun Yan <yanzhirun_163@163.com>, Ziyang Xuan <xuanziyang2@huawei.com>, Tyler Retzlaff <roretzla@linux.microsoft.com> Subject: [PATCH v2 58/83] crypto/ipsec_mb: move alignment attribute on types Date: Mon, 15 Apr 2024 13:04:20 -0700 Message-Id: <1713211485-9021-59-git-send-email-roretzla@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1713211485-9021-1-git-send-email-roretzla@linux.microsoft.com> References: <1710949096-5786-1-git-send-email-roretzla@linux.microsoft.com> <1713211485-9021-1-git-send-email-roretzla@linux.microsoft.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org Move location of __rte_aligned(a) to new conventional location. The new placement between {struct,union} and the tag allows the desired alignment to be imparted on the type regardless of the toolchain being used for both C and C++. Additionally, it avoids confusion by Doxygen when generating documentation. Signed-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com> Acked-by: Morten Brørup <mb@smartsharesystems.com> --- drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 4 ++-- drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h | 24 ++++++++++++------------ drivers/crypto/ipsec_mb/pmd_chacha_poly_priv.h | 4 ++-- drivers/crypto/ipsec_mb/pmd_kasumi_priv.h | 4 ++-- drivers/crypto/ipsec_mb/pmd_snow3g_priv.h | 4 ++-- drivers/crypto/ipsec_mb/pmd_zuc_priv.h | 4 ++-- 6 files changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c index 4de4866..69a5466 100644 --- a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c +++ b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c @@ -32,8 +32,8 @@ struct aesni_mb_op_buf_data { { uint32_t i, length; - uint8_t ipad_buf[blocksize] __rte_aligned(16); - uint8_t opad_buf[blocksize] __rte_aligned(16); + alignas(16) uint8_t ipad_buf[blocksize]; + alignas(16) uint8_t opad_buf[blocksize]; /* Setup inner and outer pads */ memset(ipad_buf, HMAC_IPAD_VALUE, blocksize); diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h b/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h index 85994fe..eec8931 100644 --- a/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h +++ b/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h @@ -848,7 +848,7 @@ struct aesni_mb_qp_data { } /** AES-NI multi-buffer private session structure */ -struct aesni_mb_session { +struct __rte_cache_aligned aesni_mb_session { IMB_JOB template_job; /*< Template job structure */ uint32_t session_id; @@ -869,9 +869,9 @@ struct aesni_mb_session { struct { union { struct { - uint32_t encode[60] __rte_aligned(16); + alignas(16) uint32_t encode[60]; /* *< encode key */ - uint32_t decode[60] __rte_aligned(16); + alignas(16) uint32_t decode[60]; /* *< decode key */ } expanded_aes_keys; /* *< Expanded AES keys - Allocating space to @@ -903,9 +903,9 @@ struct aesni_mb_session { /* *< auth operation generate or verify */ union { struct { - uint8_t inner[128] __rte_aligned(16); + alignas(16) uint8_t inner[128]; /* *< inner pad */ - uint8_t outer[128] __rte_aligned(16); + alignas(16) uint8_t outer[128]; /* *< outer pad */ } pads; /* *< HMAC Authentication pads - @@ -915,20 +915,20 @@ struct aesni_mb_session { */ struct { - uint32_t k1_expanded[44] __rte_aligned(16); + alignas(16) uint32_t k1_expanded[44]; /* *< k1 (expanded key). */ - uint8_t k2[16] __rte_aligned(16); + alignas(16) uint8_t k2[16]; /* *< k2. */ - uint8_t k3[16] __rte_aligned(16); + alignas(16) uint8_t k3[16]; /* *< k3. */ } xcbc; struct { - uint32_t expkey[60] __rte_aligned(16); + alignas(16) uint32_t expkey[60]; /* *< k1 (expanded key). */ - uint32_t skey1[4] __rte_aligned(16); + alignas(16) uint32_t skey1[4]; /* *< k2. */ - uint32_t skey2[4] __rte_aligned(16); + alignas(16) uint32_t skey2[4]; /* *< k3. */ } cmac; /* *< Expanded XCBC authentication keys */ @@ -943,7 +943,7 @@ struct aesni_mb_session { uint16_t req_digest_len; } auth; -} __rte_cache_aligned; +}; typedef void (*hash_one_block_t)(const void *data, void *digest); typedef void (*aes_keyexp_t)(const void *key, void *enc_exp_keys, diff --git a/drivers/crypto/ipsec_mb/pmd_chacha_poly_priv.h b/drivers/crypto/ipsec_mb/pmd_chacha_poly_priv.h index 842f62f..0eca63c 100644 --- a/drivers/crypto/ipsec_mb/pmd_chacha_poly_priv.h +++ b/drivers/crypto/ipsec_mb/pmd_chacha_poly_priv.h @@ -46,7 +46,7 @@ struct rte_cryptodev_capabilities chacha20_poly1305_capabilities[] = { uint8_t pmd_driver_id_chacha20_poly1305; /** CHACHA20 POLY1305 private session structure */ -struct chacha20_poly1305_session { +struct __rte_cache_aligned chacha20_poly1305_session { struct { uint16_t length; uint16_t offset; @@ -60,7 +60,7 @@ struct chacha20_poly1305_session { /**< Generated digest length */ uint8_t key[CHACHA20_POLY1305_KEY_SIZE]; enum ipsec_mb_operation op; -} __rte_cache_aligned; +}; struct chacha20_poly1305_qp_data { struct chacha20_poly1305_context_data chacha20_poly1305_ctx_data; diff --git a/drivers/crypto/ipsec_mb/pmd_kasumi_priv.h b/drivers/crypto/ipsec_mb/pmd_kasumi_priv.h index 8db1d1c..c2e28ea 100644 --- a/drivers/crypto/ipsec_mb/pmd_kasumi_priv.h +++ b/drivers/crypto/ipsec_mb/pmd_kasumi_priv.h @@ -61,14 +61,14 @@ }; /** KASUMI private session structure */ -struct kasumi_session { +struct __rte_cache_aligned kasumi_session { /* Keys have to be 16-byte aligned */ kasumi_key_sched_t pKeySched_cipher; kasumi_key_sched_t pKeySched_hash; enum ipsec_mb_operation op; enum rte_crypto_auth_operation auth_op; uint16_t cipher_iv_offset; -} __rte_cache_aligned; +}; struct kasumi_qp_data { uint8_t temp_digest[KASUMI_DIGEST_LENGTH]; diff --git a/drivers/crypto/ipsec_mb/pmd_snow3g_priv.h b/drivers/crypto/ipsec_mb/pmd_snow3g_priv.h index ca1ce7f..9492a0b 100644 --- a/drivers/crypto/ipsec_mb/pmd_snow3g_priv.h +++ b/drivers/crypto/ipsec_mb/pmd_snow3g_priv.h @@ -65,14 +65,14 @@ }; /** SNOW 3G private session structure */ -struct snow3g_session { +struct __rte_cache_aligned snow3g_session { enum ipsec_mb_operation op; enum rte_crypto_auth_operation auth_op; snow3g_key_schedule_t pKeySched_cipher; snow3g_key_schedule_t pKeySched_hash; uint16_t cipher_iv_offset; uint16_t auth_iv_offset; -} __rte_cache_aligned; +}; struct snow3g_qp_data { uint8_t temp_digest[SNOW3G_DIGEST_LENGTH]; diff --git a/drivers/crypto/ipsec_mb/pmd_zuc_priv.h b/drivers/crypto/ipsec_mb/pmd_zuc_priv.h index 76fd675..a17a65a 100644 --- a/drivers/crypto/ipsec_mb/pmd_zuc_priv.h +++ b/drivers/crypto/ipsec_mb/pmd_zuc_priv.h @@ -64,14 +64,14 @@ }; /** ZUC private session structure */ -struct zuc_session { +struct __rte_cache_aligned zuc_session { enum ipsec_mb_operation op; enum rte_crypto_auth_operation auth_op; uint8_t pKey_cipher[ZUC_IV_KEY_LENGTH]; uint8_t pKey_hash[ZUC_IV_KEY_LENGTH]; uint16_t cipher_iv_offset; uint16_t auth_iv_offset; -} __rte_cache_aligned; +}; struct zuc_qp_data { -- 1.8.3.1