From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3FC064404F; Wed, 12 Jun 2024 17:27:21 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C944D4332E; Wed, 12 Jun 2024 17:07:24 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mails.dpdk.org (Postfix) with ESMTP id A81784330C for ; Wed, 12 Jun 2024 17:07:12 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718204833; x=1749740833; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3fenKERk88joePyAZMBa3vH9m2pvnBvSizC0WTiczKY=; b=mU54RAL8V0yUuuhyRpuLFlLaDRnTtT8+MesaBFEGGoRru7bmQb70ABCB l9K1weQhJvNiOt66+WfrdhKQlN3y4HBT3Capcyb3VoP+QcpCPXuDUjuA/ 425KE0L2NWcxy5vW8IHr3QCBJ8fPZZmMUGhsv90ENY3YakRFrOtyRwutu z5ARqTAlIo9Ivc4qv6713XT0VizkZJCv76YlSgXYwUpLas2wF+bDGOu0B DQc6gpT4NmpD4Ka3yyudA39ISd4iQcNpEu6/x8qdaxNAzW6c3zI4voPEg rKXgQzwYpwNT07QAmbzFbjbNfsUzDIYh8I4bMRpaF+iKs+b1zomw1wFl6 A==; X-CSE-ConnectionGUID: p4zEFX8ARe+4cWb99JoASg== X-CSE-MsgGUID: mDeO3FaDTHOkqvePRY8Djg== X-IronPort-AV: E=McAfee;i="6700,10204,11101"; a="32460171" X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="32460171" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2024 08:07:12 -0700 X-CSE-ConnectionGUID: EKdylwBVTVqbRd/xo9wb1A== X-CSE-MsgGUID: jjvk3mcER0WavSkfB3VayA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="39926076" Received: from silpixa00401119.ir.intel.com ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 12 Jun 2024 08:07:11 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Ian Stokes , bruce.richardson@intel.com, Karol Kolacinski , Jacob Keller Subject: [PATCH v2 141/148] net/ice/base: cleanup timestamp registers correctly Date: Wed, 12 Jun 2024 16:02:15 +0100 Message-ID: <175452d277d9d5555d8c39f219564c46b6637f75.1718204529.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: <20240430154014.1026-1-ian.stokes@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Ian Stokes E822 PHY TS registers should not be written and the only way to cleanup them is to reset QUAD memory. To ensure that the status bit for the timestamp index is cleared, ensure that ice_clear_phy_tstamp implementations first read the timestamp out. Implementations which can write the register continue to do so. Add a note to indicate this function should only be called on timestamps which have their valid bit set. Signed-off-by: Karol Kolacinski Signed-off-by: Jacob Keller Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_ptp_hw.c | 63 +++++++++++++++++-------------- 1 file changed, 34 insertions(+), 29 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index cfcbdddee8..b351784f4a 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -1554,8 +1554,18 @@ static int ice_clear_phy_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx) { int err; + u64 unused_tstamp; u16 lo_addr; + /* Read the timestamp register to ensure the timestamp status bit is + * cleared. + */ + err = ice_read_phy_tstamp_eth56g(hw, port, idx, &unused_tstamp); + if (err) { + ice_debug(hw, ICE_DBG_PTP, "Failed to read the PHY timestamp register for port %u, idx %u, err %d\n", + port, idx, err); + } + lo_addr = (u16)PHY_TSTAMP_L(idx); err = ice_phy_port_mem_write_eth56g(hw, port, lo_addr, 0); @@ -2955,25 +2965,16 @@ ice_read_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp) * This function should only be called on an idx whose bit is set according to * ice_get_phy_tx_tstamp_ready(). */ -static int ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx) +static int +ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx) { + u64 unused_tstamp; int err; - u16 lo_addr, hi_addr; - lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx); - hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx); - - err = ice_write_quad_reg_e822(hw, quad, lo_addr, 0); - if (err) { - ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, err %d\n", - err); - return err; - } - - err = ice_write_quad_reg_e822(hw, quad, hi_addr, 0); + err = ice_read_phy_tstamp_e822(hw, quad, idx, &unused_tstamp); if (err) { - ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, err %d\n", - err); + ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for quad %u, idx %u, err %d\n", + quad, idx, err); return err; } @@ -4902,40 +4903,44 @@ ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) } /** - * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block + * ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY * @hw: pointer to the HW struct * @lport: the lport to read from * @idx: the timestamp index to reset * - * Clear a timestamp from the timestamp block, discarding its value without - * returning it. This resets the memory err bit for the timestamp index - * allowing it to be reused for another timestamp in the future. + * Read the timestamp and then forcibly overwrite its value to clear the valid + * bit from the timestamp block of the external PHY on the E810 device. * - * For E822 devices, the block number is the PHY quad to clear from. For E810 - * devices, the block number is the logical port to clear from. - * - * This function must only be called on a timestamp index whose valid bit is - * set according to ice_get_phy_tx_tstamp_ready(). + * This function should only be called on an idx whose bit is set according to + * ice_get_phy_tx_tstamp_ready(). */ static int ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx) { - int err; u32 lo_addr, hi_addr; + u64 unused_tstamp; + int err; + + err = ice_read_phy_tstamp_e810(hw, lport, idx, &unused_tstamp); + if (err) { + ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for lport %u, idx %u, err %d\n", + lport, idx, err); + return err; + } lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); err = ice_write_phy_reg_e810(hw, lo_addr, 0); if (err) { - ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, err %d\n", - err); + ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for lport %u, idx %u, err %d\n", + lport, idx, err); return err; } err = ice_write_phy_reg_e810(hw, hi_addr, 0); if (err) { - ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, err %d\n", - err); + ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register for lport %u, idx %u, err %d\n", + lport, idx, err); return err; } -- 2.43.0