From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out1-smtp.messagingengine.com (out1-smtp.messagingengine.com [66.111.4.25]) by dpdk.org (Postfix) with ESMTP id 9B01B1B416 for ; Wed, 9 Jan 2019 12:28:23 +0100 (CET) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id 078ED2448F; Wed, 9 Jan 2019 06:28:23 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute1.internal (MEProxy); Wed, 09 Jan 2019 06:28:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=mesmtp; bh=uD1RvkVHsm84GsgTKpFdJkmiTC98gam12ssPIEg1cFQ=; b=kEea4Gc67aOD QOIIcpwkHIkSrN3kvXgRjoWYVQ6tZyB4gDHVaK89F1683oSxv153jPADZOa2s6FN G2ZyQyd09U16pd4htVKKIxFi/hSnt5Y+SCMH2Dr5iKQmdNzR68j6Pv++1Yh8w676 Ioz5N01f8se/MF3JLC9dmTJry6AfdQQ= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=uD1RvkVHsm84GsgTKpFdJkmiTC98gam12ssPIEg1c FQ=; b=v1zsSS0K/TjK7a/9PsAeJIoZMnOx9c0L715ZJxGDJSAOMRn6foRQqqDoj tUb2obq8FwXqcAUqhvwgF2+qQvbhxlcINQbJQ+ht4/Y6FFkWlc4a8+6G2YHPeu31 Te3P4R/ZAw/QV7UIL5Karwsb9fKf2+JxPRf5GSKx9gNAvRL8gn7POlXe0r5E0GGp n9H2CWwdr0Mn9H/WvAsgmimNATILvi1g88ty+/utASZbgGAVusfKWBK63tK5WcqH Enobr4ymvhg65edejNKzqzkkWuPg1uCBNgriaHmb6yLlXKxv1vXMO024tUVcM8jM P3TT6QwvEZHzUgtydapUEYfV9V1Fg== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedtledrfedugddvkeculddtuddrgedtkedrtddtmd cutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfhuthen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkfgjfhgggfgtsehtufertddttddvnecuhfhrohhmpefvhhhomhgr shcuofhonhhjrghlohhnuceothhhohhmrghssehmohhnjhgrlhhonhdrnhgvtheqnecukf hppeejjedrudefgedrvddtfedrudekgeenucfrrghrrghmpehmrghilhhfrhhomhepthhh ohhmrghssehmohhnjhgrlhhonhdrnhgvthenucevlhhushhtvghrufhiiigvpedt X-ME-Proxy: Received: from xps.localnet (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id 47D00E435E; Wed, 9 Jan 2019 06:28:21 -0500 (EST) From: Thomas Monjalon To: Jerin Jacob Kollanukkaran , "yskoh@mellanox.com" Cc: "shahafs@mellanox.com" , "Gavin.Hu@arm.com" , "bluca@debian.org" , "dev@dpdk.org" , honnappa.nagarahalli@arm.com, Thomas Speier Date: Wed, 09 Jan 2019 12:28:20 +0100 Message-ID: <1764937.rquPbBeTJo@xps> In-Reply-To: <15db28a8a28845f20ab9f5da1782f3c62fc7db80.camel@marvell.com> References: <20190109093915.40882-1-yskoh@mellanox.com> <0F6E5E54-EC4A-42AD-AF67-D901802F24E3@mellanox.com> <15db28a8a28845f20ab9f5da1782f3c62fc7db80.camel@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [EXT] [PATCH] config: change default cache line size for ARMv8 with meson X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 09 Jan 2019 11:28:23 -0000 09/01/2019 11:49, Jerin Jacob Kollanukkaran: > On Wed, 2019-01-09 at 10:22 +0000, Yongseok Koh wrote: > > On Jan 9, 2019, at 2:09 AM, Jerin Jacob Kollanukkaran wrote: > > > I think, I way forward is to add config/arm/arm64_a72_linuxapp_gcc > > > for meson. This config can be used for all SoC with A72 armv8 > > > implementation and may have sym link to specfific SoC to avoid > > > confusion to end users. > > > > Is config/arm/arm64_a72_linuxapp_gcc valid? Others have > > Yes. For cross compiling for A72. Any cross-compilation with meson requires a config file. The default Arm cross-compilation is done with config/arm/arm64_armv8_linuxapp_gcc which set implementor_id = 'generic' For native compilation, implementor_id is detected from /sys/devices/system/cpu/cpu0/regs/identification/midr_el1 So each Arm machine needs 2 things: - a cross-compilation file - settings based on implementor_id in config/arm/meson.build > Having not seperate IMPLEMENTOR ID is a chip design issue. No I don't think it's a design issue. If the Arm core has no modification, it does not need to be specially identified. > I think it can work around by creating > config/arm/arm64__linuxapp_gcc > and build on x86 or arm64 through > > meson build --cross-file config/arm/arm64__linuxapp_gcc No, it is a real A72, so it should work with default settings. The only issue we have is that the default cache line size for Aarch64 is set to 128 in config/arm/meson.build, and this is wrong. The default cache line is 64 bits. This is already overriden for Cavium machines which have 128-bit cache lines. It may be needed to do the same change for other machines (Qualcomm?) having Arm core modified to 128-bit cache lines. The other concern is about running a generic Arm build. Given 64-bit should be the default, generic builds will have this value. Is it a big issue for running generic 64-bit build on Cavium machines?