From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wi0-f181.google.com (mail-wi0-f181.google.com [209.85.212.181]) by dpdk.org (Postfix) with ESMTP id 9D59AC3B4 for ; Fri, 10 Jul 2015 16:52:45 +0200 (CEST) Received: by wicmv11 with SMTP id mv11so16034397wic.1 for ; Fri, 10 Jul 2015 07:52:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:organization :user-agent:in-reply-to:references:mime-version :content-transfer-encoding:content-type; bh=DkL8X49i+Dsz4HrAV+W+honCW2uUkktVrw/pOka2pfo=; b=GQ4crz5F4I5/pUuOSNcvzA6uqwA4njrLz+g4Smq078b5skXQWM2YikNDow1XICX//2 kI0+/8qzBpMzaFMCZPmXscG/QUFZun5X8CaJebNI3jkXKhZNXijs02DACf+2j8EPCF2N oDYdzhi+mA0NnNHfxA2jngk98nrIm5p0SiQDK4fq1AXaN5LorKmrASDCtHWyXxikzGEG DKVshK91b0ODEgaxZN1wqvxUpB269m/nFLj+QGmHw2u/yJ7/ZpdYhdJxn7obRLMkA6lL 4pUcDisSpWT8Wp59PC4Xe/A7wI2kHWOOuIc8hMg1TwuxhurLqOqoKMORhLKe5MSCEgYD ujzA== X-Gm-Message-State: ALoCoQl1oy690gst0HdWWpjQtWASOVOf54e3ODDivXkKIQppeHCr6ki/XVxFrLDKvqT+6a7+9Rtq X-Received: by 10.194.78.84 with SMTP id z20mr43448359wjw.141.1436539965495; Fri, 10 Jul 2015 07:52:45 -0700 (PDT) Received: from xps13.localnet (136-92-190-109.dsl.ovh.fr. [109.190.92.136]) by smtp.gmail.com with ESMTPSA id az1sm8679122wib.0.2015.07.10.07.52.41 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Jul 2015 07:52:44 -0700 (PDT) From: Thomas Monjalon To: xuelin.shi@freescale.com Date: Fri, 10 Jul 2015 16:51:34 +0200 Message-ID: <1774489.naxWROzf8E@xps13> Organization: 6WIND User-Agent: KMail/4.14.8 (Linux/4.0.4-2-ARCH; KDE/4.14.8; x86_64; ; ) In-Reply-To: <2601191342CEEE43887BDE71AB97725821415A5B@irsmsx105.ger.corp.intel.com> References: <1427786750-30308-1-git-send-email-xuelin.shi@freescale.com> <2601191342CEEE43887BDE71AB97725821415A5B@irsmsx105.ger.corp.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Cc: dev@dpdk.org Subject: Re: [dpdk-dev] [PATCH v3] ixgbe: fix data access on big endian cpu X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 10 Jul 2015 14:52:45 -0000 Xuelin, have you given up with that patch? 2015-04-14 23:11, Ananyev, Konstantin: > From: xuelin.shi@freescale.com [mailto:xuelin.shi@freescale.com] > > txd->read.olinfo_status = > > - rte_cpu_to_le_32(olinfo_status); > > + rte_cpu_to_le_32(olinfo_status); > > + > > Not sure, what had changed here? > > @@ -2293,7 +2314,8 @@ ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) > > rxdp = &(rxq->rx_ring[rxq->rx_tail]); > > > > while ((desc < rxq->nb_rx_desc) && > > - (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) { > > + (rte_le_to_cpu_32(rxdp->wb.upper.status_error) & > > + IXGBE_RXDADV_STAT_DD)) { > > Why not ' rxdp->wb.upper.status_error & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)'? > To keep it consistent with rest of the changes?