From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D0A9B4404F; Wed, 12 Jun 2024 17:09:25 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 85D0242793; Wed, 12 Jun 2024 17:03:58 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mails.dpdk.org (Postfix) with ESMTP id CC6874270A for ; Wed, 12 Jun 2024 17:03:55 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718204636; x=1749740636; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lzQzAqJLVih0HbpfpP0xQ/0UCbGmYXshWbJaat+FFbc=; b=OTrYGadao4o6MRKIOzn4ouhohk5jH26KorPdLbaRp4awOA/XA4v+lXIn mjXTjgv5WL5kbQaBQpTXMZXsKKy/YPU+sGCUcSn53uW2gjkp6bixmPd+p 7Gk/tDcAWQKctuvoJGn4O1zHggzg9Z1xlMTLIgLnNcb5aCQAQFMAh4BNg d3XovqI5Z3UZFnckZvMPFLZY9elJiA5pHjZMtHsA4FrWYXgdECyUg83um x0pGfrny0Yh1lfcov2vBwCbKAx6W4mIvnfi1hw/GGU57l64RqJHyk8RoO jedTZpsJ5P1o4QPIt+cFeCrphXTpUmdepJSDFJ9qza/sf1zXZaxJE1zLo w==; X-CSE-ConnectionGUID: yqjWnnLZRY2Y0REPNzWYNA== X-CSE-MsgGUID: XVcmNFVtRhimxZq2scdOgA== X-IronPort-AV: E=McAfee;i="6700,10204,11101"; a="32459255" X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="32459255" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2024 08:03:55 -0700 X-CSE-ConnectionGUID: PnnaoyqkSsyjs6JicwtA1Q== X-CSE-MsgGUID: IfJXMaUKTrmclCGNWhQwUQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="39924978" Received: from silpixa00401119.ir.intel.com ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 12 Jun 2024 08:03:54 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Ian Stokes , bruce.richardson@intel.com, Karol Kolacinski Subject: [PATCH v2 024/148] net/ice/base: add LL Tx timestamp interrupt read Date: Wed, 12 Jun 2024 16:00:18 +0100 Message-ID: <17a844cf0c506476f9bf079c75a5268855aff599.1718204528.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: <20240430154014.1026-1-ian.stokes@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Ian Stokes E810 products can support low latency Tx timestamp register read using the SW interrupt from the FW. Add a check for the device capability and use the new method if supported. Signed-off-by: Karol Kolacinski Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_common.c | 3 +++ drivers/net/ice/base/ice_ptp_hw.h | 1 + drivers/net/ice/base/ice_type.h | 2 ++ 3 files changed, 6 insertions(+) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index c3d429828d..1f98034c55 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -2783,6 +2783,7 @@ ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0); + info->ts_ll_int_read = ((number & ICE_TS_LL_TX_TS_INT_READ_M) != 0); info->tmr_own_map = phys_id; @@ -2802,6 +2803,8 @@ ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, info->tmr1_ena); ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n", info->ts_ll_read); + ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_int_read = %u\n", + info->ts_ll_int_read); ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", info->tmr_own_map); } diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 35ab9bb3e8..441ad0b77d 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -489,6 +489,7 @@ int ice_ptp_init_phy_cfg(struct ice_hw *hw); /* Tx timestamp low latency read definitions */ #define TS_LL_READ_RETRIES 200 +#define TS_LL_READ_TS_INTR BIT(30) #define TS_LL_READ_TS BIT(31) #define TS_LL_READ_TS_IDX_S 24 #define TS_LL_READ_TS_IDX_M MAKEMASK(0x3F, 0) diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index 239b1a018e..7a1471e474 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -778,6 +778,7 @@ struct ice_ts_func_info { #define ICE_TS_TMR0_ENA_M BIT(25) #define ICE_TS_TMR1_ENA_M BIT(26) #define ICE_TS_LL_TX_TS_READ_M BIT(28) +#define ICE_TS_LL_TX_TS_INT_READ_M BIT(29) struct ice_ts_dev_info { /* Device specific info */ @@ -790,6 +791,7 @@ struct ice_ts_dev_info { u8 tmr0_ena : 1; u8 tmr1_ena : 1; u8 ts_ll_read : 1; + u8 ts_ll_int_read : 1; }; #define ICE_NAC_TOPO_PRIMARY_M BIT(0) -- 2.43.0