From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 68A1FA04BB; Tue, 6 Oct 2020 23:49:53 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 086EE2952; Tue, 6 Oct 2020 23:49:51 +0200 (CEST) Received: from out3-smtp.messagingengine.com (out3-smtp.messagingengine.com [66.111.4.27]) by dpdk.org (Postfix) with ESMTP id 1C9821E35 for ; Tue, 6 Oct 2020 23:49:48 +0200 (CEST) Received: from compute2.internal (compute2.nyi.internal [10.202.2.42]) by mailout.nyi.internal (Postfix) with ESMTP id B00ED5C0192; Tue, 6 Oct 2020 17:49:47 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute2.internal (MEProxy); Tue, 06 Oct 2020 17:49:47 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=fm2; bh= KwkDysNuM406uNb0wJuNorKJ1qaohpL9q9tacZC23PY=; b=KQzj8HBLRTOPyRxy 8UW74H5RKd4TSs/AEXQfa4qZI97B6D7Pan0wrzSb/a7l3izYL28kWpheIgnbQ9ph oCLK1ggsGqbMFIUOXmlLT6rkKZyUpyTeowH5smTxgbmOFswA/GV0JJsTMrkLkCtN lij7FzMUoWmPu5EgSg5gj0YVuffBKzmsVJQSuku2Ioro/Q7fI/islxbghL3bg5QF gnzhR12PZKztvwYwcDFlsAsnefiAI8SvuB6xgtFyPAPF1GEgZN+fr8b279Ig2hKP POakPDYYe3nZlRBszIC5ZvzB6GDF+/uuzlvlseM3sjEuypoGWQQ9p9u66DL2S7C6 H5fOpg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=KwkDysNuM406uNb0wJuNorKJ1qaohpL9q9tacZC23 PY=; b=YwRQmZf9xdqaPP1tCYdAZvOWF5t7sy8H1diqRxvwSzbZHauUS3FFFnKPv /roIFHI5xjKgWpQPtNlNHrNgb0Nx/VZxR43cmpCA+zSByjhK8FdcDv1xcbrjNKlX Ukqr8MF7vt283BzW2BLYniY0q8TnEHBz0GWy1e/HxNaPkNjhmhzz/3j4LG7RZBuV mrcRVenQGKa2zEw5AwqhG32F1Y2hbGXAlP9hAOOdA05biD0ZDaDoFHk2CXuEHisx u4009EmIzMz3GD/FLDOHv90h4d+hr+2oYL0lBJKaQF8P17EQW61yGuWKVcM0B8NK AaTUVWT/a/IEx9WbCd0Le93ZAZUmQ== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedujedrgeehgddtvdcutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvffufffkjghfggfgtgesthfuredttddtvdenucfhrhhomhepvfhhohhmrghs ucfoohhnjhgrlhhonhcuoehthhhomhgrshesmhhonhhjrghlohhnrdhnvghtqeenucggtf frrghtthgvrhhnpeevtedtkeehgeehuefgiefhgfekueeludeuieegtdelffeuueegtefg veegfeehheenucffohhmrghinheprghrmhdrtghomhenucfkphepjeejrddufeegrddvtd efrddukeegnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhho mhepthhhohhmrghssehmohhnjhgrlhhonhdrnhgvth X-ME-Proxy: Received: from xps.localnet (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id 71457306467D; Tue, 6 Oct 2020 17:49:46 -0400 (EDT) From: Thomas Monjalon To: Phil Yang , Diogo Behrens , Honnappa Nagarahalli Cc: dev@dpdk.org, nd Date: Tue, 06 Oct 2020 23:49:45 +0200 Message-ID: <1947647.zX4bR4m4Ni@thomas> In-Reply-To: References: <20200826092002.19395-1-diogo.behrens@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [PATCH] librte_eal: fix mcslock hang on weak memory X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" 31/08/2020 20:45, Honnappa Nagarahalli: > > Hi Diogo, > > Thanks for your explanation. > > As documented in https://developer.arm.com/documentation/ddi0487/fc B2.9.5 Load-Exclusive and Store-Exclusive instruction usage restrictions: > " Between the Load-Exclusive and the Store-Exclusive, there are no explicit memory accesses, preloads, > direct or indirect System register writes, address translation instructions, cache or TLB maintenance > instructions, exception generating instructions, exception returns, or indirect branches." > [Honnappa] This is a requirement on the software, not on the micro-architecture. > We are having few discussions internally, will get back soon. > > So it is not allowed to insert (1) & (4) between (2, 3). The cmpxchg operation is atomic. Please what is the conclusion?