From: "Liu, Jijiang" <jijiang.liu@intel.com>
To: Olivier MATZ <olivier.matz@6wind.com>, "dev@dpdk.org" <dev@dpdk.org>
Subject: Re: [dpdk-dev] [PATCH 0/3] i40e VXLAN TX checksum rework
Date: Thu, 27 Nov 2014 12:06:14 +0000 [thread overview]
Message-ID: <1ED644BD7E0A5F4091CF203DAFB8E4CC01D9EE2E@SHSMSX101.ccr.corp.intel.com> (raw)
In-Reply-To: <5476F919.9030906@6wind.com>
> -----Original Message-----
> From: Olivier MATZ [mailto:olivier.matz@6wind.com]
> Sent: Thursday, November 27, 2014 6:13 PM
> To: Liu, Jijiang; dev@dpdk.org
> Subject: Re: [dpdk-dev] [PATCH 0/3] i40e VXLAN TX checksum rework
>
>
> >> We have got some feedback about backward compatibility of VXLAN TX
> >> checksum offload API with 1G/10G NIC after the i40e VXLAN TX checksum
> >> codes were applied, so we have to rework the APIs on i40e, including
> >> the changes of mbuf, i40e PMD and csum engine.
> >>
> >> The main changes in mbuf are as follows, In place of removing
> >> PKT_TX_VXLAN_CKSUM, we introducing 2 new flags:
> >> PKT_TX_OUT_IP_CKSUM, PKT_TX_UDP_TUNNEL_PKT, and a new field:
> l4_tun_len.
> >
> > What about PKT_TX_OUT_UDP_CKSUM instead of
> PKT_TX_UDP_TUNNEL_PKT? It's
> > maybe more coherent with the other names.
>
> oh I just realized that the flag is not for asking to the hardware to calculate the
> outer UDP checksum.
> So why does the hardware need this information?
As I said before, this flag is used to tell FVL that the transmit packet is a UDP tunneling packet.
In FVL, there is a register need to configured, see below.
L4 Tunneling Type (Teredo / GRE header / VXLAN header) indication:
00b - No UDP / GRE tunneling (field must be set to zero if EIPT equals to zero)
01b - UDP tunneling header (Any UDP tunneling, VxLAN and Geneve)
10b - GRE tunneling header
Else - reserved
next prev parent reply other threads:[~2014-11-27 12:06 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-27 8:18 Jijiang Liu
2014-11-27 8:18 ` [dpdk-dev] [PATCH 1/3] mbuf:add two TX offload flags and change three fields Jijiang Liu
2014-11-27 10:00 ` Olivier MATZ
2014-11-27 13:14 ` Liu, Jijiang
2014-11-28 9:17 ` Olivier MATZ
[not found] ` <1ED644BD7E0A5F4091CF203DAFB8E4CC01D9EEA0@SHSMSX101.ccr.corp.intel.com>
2014-11-27 14:56 ` Ananyev, Konstantin
2014-11-27 17:01 ` Ananyev, Konstantin
2014-11-28 10:45 ` Olivier MATZ
2014-11-28 11:16 ` Ananyev, Konstantin
2014-11-30 14:50 ` Ananyev, Konstantin
2014-12-01 2:30 ` Liu, Jijiang
2014-12-01 9:52 ` Olivier MATZ
2014-12-01 11:58 ` Ananyev, Konstantin
2014-12-01 12:28 ` Olivier MATZ
2014-12-01 13:07 ` Liu, Jijiang
2014-12-01 14:31 ` Ananyev, Konstantin
2014-11-27 8:18 ` [dpdk-dev] [PATCH 2/3] i40e:PMD change for VXLAN TX checksum Jijiang Liu
2014-11-27 8:18 ` [dpdk-dev] [PATCH 3/3] testpmd:rework csum forward engine Jijiang Liu
2014-11-27 10:23 ` Olivier MATZ
2014-11-27 8:50 ` [dpdk-dev] [PATCH 0/3] i40e VXLAN TX checksum rework Liu, Jijiang
2014-11-27 9:44 ` Olivier MATZ
2014-11-27 10:12 ` Olivier MATZ
2014-11-27 12:06 ` Liu, Jijiang [this message]
2014-11-27 12:07 ` Liu, Jijiang
2014-11-27 15:29 ` Ananyev, Konstantin
2014-11-27 16:31 ` Liu, Jijiang
2014-12-03 8:02 ` Liu, Jijiang
2014-11-28 9:26 ` Olivier MATZ
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