From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id E46FB2A9 for ; Thu, 27 Nov 2014 13:06:37 +0100 (CET) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 27 Nov 2014 04:06:36 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.07,469,1413270000"; d="scan'208";a="639018460" Received: from kmsmsx152.gar.corp.intel.com ([172.21.73.87]) by fmsmga002.fm.intel.com with ESMTP; 27 Nov 2014 04:06:17 -0800 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by KMSMSX152.gar.corp.intel.com (172.21.73.87) with Microsoft SMTP Server (TLS) id 14.3.195.1; Thu, 27 Nov 2014 20:06:17 +0800 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.110]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.182]) with mapi id 14.03.0195.001; Thu, 27 Nov 2014 20:06:16 +0800 From: "Liu, Jijiang" To: Olivier MATZ , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH 0/3] i40e VXLAN TX checksum rework Thread-Index: AQHQChvO5Hbj694uHUagPyQ5KbGpNZxzszuAgAAHzICAAKOxUA== Date: Thu, 27 Nov 2014 12:06:14 +0000 Message-ID: <1ED644BD7E0A5F4091CF203DAFB8E4CC01D9EE2E@SHSMSX101.ccr.corp.intel.com> References: <1417076319-629-1-git-send-email-jijiang.liu@intel.com> <5476F28F.7010802@6wind.com> <5476F919.9030906@6wind.com> In-Reply-To: <5476F919.9030906@6wind.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH 0/3] i40e VXLAN TX checksum rework X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 27 Nov 2014 12:06:38 -0000 > -----Original Message----- > From: Olivier MATZ [mailto:olivier.matz@6wind.com] > Sent: Thursday, November 27, 2014 6:13 PM > To: Liu, Jijiang; dev@dpdk.org > Subject: Re: [dpdk-dev] [PATCH 0/3] i40e VXLAN TX checksum rework >=20 >=20 > >> We have got some feedback about backward compatibility of VXLAN TX > >> checksum offload API with 1G/10G NIC after the i40e VXLAN TX checksum > >> codes were applied, so we have to rework the APIs on i40e, including > >> the changes of mbuf, i40e PMD and csum engine. > >> > >> The main changes in mbuf are as follows, In place of removing > >> PKT_TX_VXLAN_CKSUM, we introducing 2 new flags: > >> PKT_TX_OUT_IP_CKSUM, PKT_TX_UDP_TUNNEL_PKT, and a new field: > l4_tun_len. > > > > What about PKT_TX_OUT_UDP_CKSUM instead of > PKT_TX_UDP_TUNNEL_PKT? It's > > maybe more coherent with the other names. >=20 > oh I just realized that the flag is not for asking to the hardware to cal= culate the > outer UDP checksum. > So why does the hardware need this information? As I said before, this flag is used to tell FVL that the transmit packet is= a UDP tunneling packet. In FVL, there is a register need to configured, see below. L4 Tunneling Type (Teredo / GRE header / VXLAN header) indication: 00b - No UDP / GRE tunneling (field must be set to zero if EIPT equals to z= ero) 01b - UDP tunneling header (Any UDP tunneling, VxLAN and Geneve) 10b - GRE tunneling header Else - reserved