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Thu, 1 Sep 2022 18:23:41 +0100 Envelope-to: junfeng.guo@intel.com, qi.z.zhang@intel.com, jingjing.wu@intel.com, dev@dpdk.org, xiaoyun.li@intel.com, awogbemila@google.com, bruce.richardson@intel.com Received: from [10.71.194.74] (port=56050) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1oTnun-0001MJ-90; Thu, 01 Sep 2022 18:23:41 +0100 Message-ID: <1d5c51a8-74b9-0a84-40f3-e5288d67fc73@xilinx.com> Date: Thu, 1 Sep 2022 18:23:41 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.2.0 Subject: Re: [PATCH v2 08/10] net/gve: add support to get dev info and configure dev Content-Language: en-US To: Junfeng Guo , , CC: , , , References: <20220729193042.2764633-2-xiaoyun.li@intel.com> <20220829084127.934183-1-junfeng.guo@intel.com> <20220829084127.934183-9-junfeng.guo@intel.com> From: Ferruh Yigit In-Reply-To: <20220829084127.934183-9-junfeng.guo@intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ef18bcad-fea4-450f-458e-08da8c3ebf13 X-MS-TrafficTypeDiagnostic: BYAPR02MB5301:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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PTR:unknown-80-198.xilinx.com; CAT:NONE; SFS:(13230016)(4636009)(346002)(136003)(376002)(39860400002)(396003)(40470700004)(36840700001)(46966006)(426003)(26005)(2906002)(82740400003)(2616005)(82310400005)(44832011)(53546011)(336012)(47076005)(40460700003)(186003)(36860700001)(40480700001)(83380400001)(316002)(8936002)(54906003)(70206006)(70586007)(4326008)(31696002)(110136005)(5660300002)(8676002)(31686004)(356005)(7636003)(41300700001)(9786002)(36756003)(478600001)(50156003)(43740500002); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Sep 2022 17:23:54.5418 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ef18bcad-fea4-450f-458e-08da8c3ebf13 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.80.198]; Helo=[xir-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT020.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR02MB5301 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On 8/29/2022 9:41 AM, Junfeng Guo wrote: > > Add dev_ops dev_infos_get. > Complete dev_configure with RX offloads configuration. > > Signed-off-by: Xiaoyun Li > Signed-off-by: Junfeng Guo > --- > drivers/net/gve/gve.h | 3 ++ > drivers/net/gve/gve_ethdev.c | 61 ++++++++++++++++++++++++++++++++++++ > 2 files changed, 64 insertions(+) > > diff --git a/drivers/net/gve/gve.h b/drivers/net/gve/gve.h > index 7f4d0e37f3..004e0a75ca 100644 > --- a/drivers/net/gve/gve.h > +++ b/drivers/net/gve/gve.h > @@ -27,6 +27,9 @@ > #define GVE_DEFAULT_TX_FREE_THRESH 256 > #define GVE_TX_MAX_FREE_SZ 512 > > +#define GVE_MIN_BUF_SIZE 1024 > +#define GVE_MAX_RX_PKTLEN 65535 > + > /* PTYPEs are always 10 bits. */ > #define GVE_NUM_PTYPES 1024 > > diff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c > index 5ebe2c30ea..6bc7bf4519 100644 > --- a/drivers/net/gve/gve_ethdev.c > +++ b/drivers/net/gve/gve_ethdev.c > @@ -96,6 +96,14 @@ gve_free_qpls(struct gve_priv *priv) > static int > gve_dev_configure(__rte_unused struct rte_eth_dev *dev) > { > + struct gve_priv *priv = dev->data->dev_private; > + > + if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) > + dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; > + > + if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) > + priv->enable_lsc = 1; What is the relation between LRO and LSC? Is it a typo? And does driver support LSC at all? Or any interrupt? > + > return 0; > } > > @@ -266,6 +274,58 @@ gve_dev_close(struct rte_eth_dev *dev) > return err; > } > > +static int > +gve_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) > +{ > + struct gve_priv *priv = dev->data->dev_private; > + > + dev_info->device = dev->device; > + dev_info->max_mac_addrs = 1; > + dev_info->max_rx_queues = priv->max_nb_rxq; > + dev_info->max_tx_queues = priv->max_nb_txq; > + dev_info->min_rx_bufsize = GVE_MIN_BUF_SIZE; > + dev_info->max_rx_pktlen = GVE_MAX_RX_PKTLEN; > + Can you please provide 'max_mtu' & 'min_mtu' values too?