From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from bilemail1.empirix.com (bilemail1.empirix.com [208.67.76.245]) by dpdk.org (Postfix) with ESMTP id 4F91A5680 for ; Fri, 28 Aug 2015 13:23:24 +0200 (CEST) Received: from BILEMAIL1.empirix.com (10.17.8.30) by bilemail1.empirix.com (10.17.8.30) with Microsoft SMTP Server (TLS) id 15.0.775.38; Fri, 28 Aug 2015 07:23:05 -0400 Received: from BILEMAIL1.empirix.com ([fe80::f9e0:9293:2523:f021]) by bilemail1.empirix.com ([fe80::f9e0:9293:2523:f021%22]) with mapi id 15.00.0775.031; Fri, 28 Aug 2015 07:23:05 -0400 From: "Montorsi, Francesco" To: "dev@dpdk.org" Thread-Topic: about new timesync feature in 2.1.0 Thread-Index: AdDhgq9LBHdW45SCT02Gh1E2zNqOhg== Date: Fri, 28 Aug 2015 11:23:04 +0000 Message-ID: <1e634e4cf86d4c58ab88923e14947a88@bilemail1.empirix.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.12.50.88] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: [dpdk-dev] about new timesync feature in 2.1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 28 Aug 2015 11:23:24 -0000 Hi, I'm very interested in getting accurate timestamps for received packets. Wh= at is the best way to do it? I found here: http://www.wand.net.nz/trac/libtrace/browser/Intel%20DPDK%20Patches/ some patch to enable timestamping but only on e1000 driver (and honestly I = don't know if that patch works with latest DPDK version!) I have tried using the timesync feature of DPDK 2.1.0 but I never get valid= RX timestamp: in my app using DPDK I call rte_eth_timesync_enable() at con= fig time and then later when a packet arrives I call rte_eth_timesync_read_= tx_timestamp(). Here's what I get:=20 .... Aug 28 11:07:48 MSP101 HwEmul[19774]: EAL: PCI memory mapped at 0x7fff800= 80000 Aug 28 11:07:48 MSP101 HwEmul[19774]: EAL: PCI memory mapped at 0x7fff801= 00000 Aug 28 11:07:48 MSP101 HwEmul[19774]: PMD: eth_ixgbe_dev_init(): MAC: 2, PH= Y: 18, SFP+: 5 Aug 28 11:07:48 MSP101 HwEmul[19774]: PMD: eth_ixgbe_dev_init(): port 2 ven= dorID=3D0x8086 deviceID=3D0x10fb Aug 28 11:07:48 MSP101 HwEmul[19774]: EAL: PCI device 0000:86:00.1 on NUMA = socket 1 Aug 28 11:07:48 MSP101 HwEmul[19774]: EAL: probe driver: 8086:10fb rte_ix= gbe_pmd Aug 28 11:07:48 MSP101 HwEmul[19774]: EAL: PCI memory mapped at 0x7fff801= 04000 Aug 28 11:07:48 MSP101 HwEmul[19774]: EAL: PCI memory mapped at 0x7fff801= 84000 Aug 28 11:07:48 MSP101 HwEmul[19774]: PMD: eth_ixgbe_dev_init(): MAC: 2, PH= Y: 15, SFP+: 10 Aug 28 11:07:48 MSP101 HwEmul[19774]: PMD: eth_ixgbe_dev_init(): port 3 ven= dorID=3D0x8086 deviceID=3D0x10fb .... Aug 28 11:07:51 MSP101 HwEmul[19774]: PMD: eth_em_rx_queue_setup(): sw_ring= =3D0x7fff62f9cfc0 hw_ring=3D0x7fff62f9d4c0 dma_addr=3D0x17a2f9d4c0 Aug 28 11:07:51 MSP101 HwEmul[19774]: PMD: eth_em_tx_queue_setup(): sw_ring= =3D0x7fff62f8ca80 hw_ring=3D0x7fff62f8cf80 dma_addr=3D0x17a2f8cf80 Aug 28 11:07:52 MSP101 HwEmul[19774]: PMD: eth_em_start(): << Aug 28 11:07:52 MSP101 HwEmul[19774]: ERROR HwEmulCaptureDPDK::init() rte_e= th_timesync_enable:err=3D-95, port=3D0: Unknown error -95 Aug 28 11:07:52 MSP101 HwEmul[19774]: ALERT HwEmulCaptureDPDK::init() Initi= alizing port 1...=20 Aug 28 11:07:52 MSP101 HwEmul[19774]: PMD: eth_em_rx_queue_setup(): sw_ring= =3D0x7fff62f7c440 hw_ring=3D0x7fff62f7c940 dma_addr=3D0x17a2f7c940 Aug 28 11:07:52 MSP101 HwEmul[19774]: PMD: eth_em_tx_queue_setup(): sw_ring= =3D0x7fff62f6bf00 hw_ring=3D0x7fff62f6c400 dma_addr=3D0x17a2f6c400 Aug 28 11:07:52 MSP101 HwEmul[19774]: PMD: eth_em_start(): << Aug 28 11:07:52 MSP101 HwEmul[19774]: ERROR HwEmulCaptureDPDK::init() rte_e= th_timesync_enable:err=3D-95, port=3D1: Unknown error -95 Aug 28 11:07:52 MSP101 HwEmul[19774]: ALERT HwEmulCaptureDPDK::init() Initi= alizing port 2...=20 Aug 28 11:07:52 MSP101 HwEmul[19774]: PMD: ixgbe_dev_rx_queue_setup(): sw_r= ing=3D0x7ffebffef6c0 sw_sc_ring=3D0x7ffebffef180 hw_ring=3D0x7ffebffefc00 d= ma_addr=3D0x2fbffefc00 Aug 28 11:07:52 MSP101 HwEmul[19774]: PMD: ixgbe_dev_tx_queue_setup(): sw_r= ing=3D0x7ffebffdebc0 hw_ring=3D0x7ffebffdf000 dma_addr=3D0x2fbffdf000 Aug 28 11:07:52 MSP101 HwEmul[19774]: PMD: ixgbe_set_tx_function(): Using s= imple tx code path Aug 28 11:07:52 MSP101 HwEmul[19774]: PMD: ixgbe_set_tx_function(): Vector = tx enabled. Aug 28 11:09:06 MSP101 HwEmul[19774]: PMD: ixgbe_set_rx_function(): Port[2]= doesn't meet Vector Rx preconditions or RTE_IXGBE_INC_VECTOR is not enable= d Aug 28 11:09:06 MSP101 HwEmul[19774]: PMD: ixgbe_set_rx_function(): Rx Burs= t Bulk Alloc Preconditions are satisfied. Rx Burst Bulk Alloc function will= be used on port=3D2. Aug 28 11:09:07 MSP101 HwEmul[19774]: PMD: ixgbe_dev_rx_queue_setup(): sw_r= ing=3D0x7ffebffce2c0 sw_sc_ring=3D0x7ffebffcdd80 hw_ring=3D0x7ffebffce800 d= ma_addr=3D0x2fbffce800 Aug 28 11:09:07 MSP101 HwEmul[19774]: PMD: ixgbe_dev_tx_queue_setup(): sw_r= ing=3D0x7ffebffbd7c0 hw_ring=3D0x7ffebffbdc00 dma_addr=3D0x2fbffbdc00 Aug 28 11:09:07 MSP101 HwEmul[19774]: PMD: ixgbe_set_tx_function(): Using s= imple tx code path Aug 28 11:09:07 MSP101 HwEmul[19774]: PMD: ixgbe_set_tx_function(): Vector = tx enabled. Aug 28 11:09:09 MSP101 HwEmul[19774]: PMD: ixgbe_set_rx_function(): Port[3]= doesn't meet Vector Rx preconditions or RTE_IXGBE_INC_VECTOR is not enable= d Aug 28 11:09:09 MSP101 HwEmul[19774]: PMD: ixgbe_set_rx_function(): Rx Burs= t Bulk Alloc Preconditions are satisfied. Rx Burst Bulk Alloc function will= be used on port=3D3. Here rte_eth_timesync_enable() failed on 2 ports (they are 1G Intel ports) = and is successful on other 2 ports. But then when I send 1 packet on the port with timesync enabled I get an er= ror from rte_eth_timesync_read_tx_timestamp(): Aug 28 13:23:18 MSP101 HwEmul[25381]: [25416] ERROR Port 3 RX timestamp reg= isters not valid: -22 Does the port need IEEE1588 messages in order to setup its timestamp regist= ers? Can I use IEEE1588 to just get some timestamp from the NIC (ideally, I woul= d like to have 1timestamp for each received packet)? Thanks a lot, Francesco Montorsi