From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3F37A4404F; Wed, 12 Jun 2024 17:12:45 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 341A142DDA; Wed, 12 Jun 2024 17:04:45 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mails.dpdk.org (Postfix) with ESMTP id 8ADEB42670 for ; Wed, 12 Jun 2024 17:04:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718204679; x=1749740679; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=H0H6cpRaifk3eNZUVWOZnuMpsiom5H1190xXgiOENxo=; b=OI2OXXca+SCJJIT86IWmwucNdkuieSAvhS2X7JOXb8VJGUe+T2D1Kyke +ZTkz+X7IOJ00O8T1x0tke+T4L6fKDDtYG6B6I6OVRQM4y6TMHZPnyrKT p+tV4HHzpTqny//dk2DGqxX4IYIqCJlmsC/LO/fru5g2MHdo2KgKGTK/N M2XGhmm11oJMEPbIuCHlLch7K9WjileJe+DbaRy9HVjUeff9OYXGNXVoX Hbn+/kc8b/V9pxAO5iWzxFlAZPszQ2W1dVs6/tZjefpHvWNA25CQ4/qxd BNLaTpXsn9Rh2WWQSEY2312hPlzbvaOu95v2YQTGEIv38eBsX+TsgoRb0 Q==; X-CSE-ConnectionGUID: Mde9/TlIQryzzxxV11B28g== X-CSE-MsgGUID: hIsPe+jxRkKBmyocDv9Nyw== X-IronPort-AV: E=McAfee;i="6700,10204,11101"; a="32459509" X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="32459509" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2024 08:04:38 -0700 X-CSE-ConnectionGUID: Z7yvMbkRSFy52SoX52bNLw== X-CSE-MsgGUID: aNzeeUQHSIyOktedUIZTBQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="39925274" Received: from silpixa00401119.ir.intel.com ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 12 Jun 2024 08:04:37 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Ian Stokes , bruce.richardson@intel.com, Jacob Keller Subject: [PATCH v2 050/148] net/ice/base: move (read|write)_sma_ctrl functions to match upstream Date: Wed, 12 Jun 2024 16:00:44 +0100 Message-ID: <1ef93b2df58e553c4f1c9cb42cee62efd72339a1.1718204528.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: <20240430154014.1026-1-ian.stokes@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Ian Stokes The upstream driver placed the ice_read_sma_ctrl_e810t and ice_write_sma_ctrl_e810t functions before the ice_read_pca9575_reg_e810t function. Align with upstream and order the functions so that the sma functions come before the pca9575 functions, slightly reducing the difference between upstream and out-of-tree. Signed-off-by: Jacob Keller Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_ptp_hw.c | 135 +++++++++++++++--------------- drivers/net/ice/base/ice_ptp_hw.h | 7 +- 2 files changed, 71 insertions(+), 71 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index db28aa308c..bd759a0e83 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -5153,70 +5153,6 @@ bool ice_is_gps_present_e810t(struct ice_hw *hw) return true; } -/** - * ice_read_pca9575_reg_e810t - * @hw: pointer to the hw struct - * @offset: GPIO controller register offset - * @data: pointer to data to be read from the GPIO controller - * - * Read the register from the GPIO controller - */ -int -ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data) -{ - struct ice_aqc_link_topo_addr link_topo; - int status; - __le16 addr; - u16 handle; - - memset(&link_topo, 0, sizeof(link_topo)); - - status = ice_get_pca9575_handle(hw, &handle); - if (status) - return status; - - link_topo.handle = CPU_TO_LE16(handle); - link_topo.topo_params.node_type_ctx = - (ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED << - ICE_AQC_LINK_TOPO_NODE_CTX_S); - - addr = CPU_TO_LE16((u16)offset); - - return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL); -} - -/** - * ice_write_pca9575_reg_e810t - * @hw: pointer to the hw struct - * @offset: GPIO controller register offset - * @data: data to be written to the GPIO controller - * - * Write the data to the GPIO controller register - */ -int -ice_write_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 data) -{ - struct ice_aqc_link_topo_addr link_topo; - __le16 addr; - int status; - u16 handle; - - memset(&link_topo, 0, sizeof(link_topo)); - - status = ice_get_pca9575_handle(hw, &handle); - if (status) - return status; - - link_topo.handle = CPU_TO_LE16(handle); - link_topo.topo_params.node_type_ctx = - (ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED << - ICE_AQC_LINK_TOPO_NODE_CTX_S); - - addr = CPU_TO_LE16((u16)offset); - - return ice_aq_write_i2c(hw, link_topo, 0, addr, 1, &data, NULL); -} - /** * ice_read_sma_ctrl_e810t * @hw: pointer to the hw struct @@ -5236,10 +5172,10 @@ int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data) *data = 0; - for (i = ICE_E810T_SMA_MIN_BIT; i <= ICE_E810T_SMA_MAX_BIT; i++) { + for (i = ICE_SMA_MIN_BIT_E810T; i <= ICE_SMA_MAX_BIT_E810T; i++) { bool pin; - status = ice_aq_get_gpio(hw, handle, i + ICE_E810T_P1_OFFSET, + status = ice_aq_get_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, &pin, NULL); if (status) break; @@ -5266,11 +5202,11 @@ int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data) if (status) return status; - for (i = ICE_E810T_SMA_MIN_BIT; i <= ICE_E810T_SMA_MAX_BIT; i++) { + for (i = ICE_SMA_MIN_BIT_E810T; i <= ICE_SMA_MAX_BIT_E810T; i++) { bool pin; pin = !(data & (1 << i)); - status = ice_aq_set_gpio(hw, handle, i + ICE_E810T_P1_OFFSET, + status = ice_aq_set_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, pin, NULL); if (status) break; @@ -5279,6 +5215,69 @@ int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data) return status; } +/** + * ice_read_pca9575_reg_e810t + * @hw: pointer to the hw struct + * @offset: GPIO controller register offset + * @data: pointer to data to be read from the GPIO controller + * + * Read the register from the GPIO controller + */ +int ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data) +{ + struct ice_aqc_link_topo_addr link_topo; + __le16 addr; + u16 handle; + int err; + + memset(&link_topo, 0, sizeof(link_topo)); + + err = ice_get_pca9575_handle(hw, &handle); + if (err) + return err; + + link_topo.handle = CPU_TO_LE16(handle); + link_topo.topo_params.node_type_ctx = + (ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED << + ICE_AQC_LINK_TOPO_NODE_CTX_S); + + addr = CPU_TO_LE16((u16)offset); + + return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL); +} + +/** + * ice_write_pca9575_reg_e810t + * @hw: pointer to the hw struct + * @offset: GPIO controller register offset + * @data: data to be written to the GPIO controller + * + * Write the data to the GPIO controller register + */ +int +ice_write_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 data) +{ + struct ice_aqc_link_topo_addr link_topo; + __le16 addr; + int status; + u16 handle; + + memset(&link_topo, 0, sizeof(link_topo)); + + status = ice_get_pca9575_handle(hw, &handle); + if (status) + return status; + + link_topo.handle = CPU_TO_LE16(handle); + link_topo.topo_params.node_type_ctx = + (ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED << + ICE_AQC_LINK_TOPO_NODE_CTX_S); + + addr = CPU_TO_LE16((u16)offset); + + return ice_aq_write_i2c(hw, link_topo, 0, addr, 1, &data, NULL); +} + /** * ice_is_pca9575_present * @hw: pointer to the hw struct diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 04556db7e9..da5acf7556 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -530,6 +530,10 @@ int ice_ptp_init_phy_cfg(struct ice_hw *hw); #define E830_HIGH_TX_MEMORY_BANK(slot, port) \ (E830_PRTTSYN_TXTIME_H(slot) + 0x8 * (port)) +#define ICE_SMA_MIN_BIT_E810T 3 +#define ICE_SMA_MAX_BIT_E810T 7 +#define ICE_PCA9575_P1_OFFSET 8 + /* E810T PCA9575 IO controller registers */ #define ICE_PCA9575_P0_IN 0x0 #define ICE_PCA9575_P1_IN 0x1 @@ -546,9 +550,6 @@ int ice_ptp_init_phy_cfg(struct ice_hw *hw); #define ICE_E810T_P1_SMA2_DIR_EN BIT(6) #define ICE_E810T_P1_SMA2_TX_EN BIT(7) -#define ICE_E810T_SMA_MIN_BIT 3 -#define ICE_E810T_SMA_MAX_BIT 7 -#define ICE_E810T_P1_OFFSET 8 /* 56G PHY quad register base addresses */ #define ICE_PHY0_BASE 0x092000 #define ICE_PHY1_BASE 0x126000 -- 2.43.0