From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pb0-f47.google.com (mail-pb0-f47.google.com [209.85.160.47]) by dpdk.org (Postfix) with ESMTP id AD252156 for ; Thu, 2 Jan 2014 17:31:34 +0100 (CET) Received: by mail-pb0-f47.google.com with SMTP id um1so14642545pbc.20 for ; Thu, 02 Jan 2014 08:32:44 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:message-id:in-reply-to :references:mime-version:content-type:content-transfer-encoding; bh=2zxHi5LTgc4JpMWyQelFFcHocnyBymdMVFvmsLAWBS4=; b=SH1aPMGiKY/Mo1NQm8eKyJav8VoO0DiCdHNIFtLHiHPXLUnv5s072JjxInKg/EEGdv Ev7feMhoNLdSyuZTDSOqn54ceL2c/YoihsCQsIr920e3hJiOtMXdSel+i4qCCo4o8CWv 8H6uURn9hiruvXBS+Hf9mfMfeTflp1kx+GjjiLY0LY9Xed264VyrY1ZsZqen5pcd+p2j 6jXVcTU16R2mZExPIUTMbUTlT999xU6uKdoumbBDaUfMz2PKer1Cj8dITodCohlOEI/N BzTLfZH15vt9ZI5wtS1DwCx6QtVmMHdnZoZLfruymVHYzkuGuCZOjcFgM5KxDVxZOF5W LCOw== X-Gm-Message-State: ALoCoQn7oWOiLNXPKNX8Jc6Q+QqpD393e5HHxZX7Ir2HkUpwhYKRO07b5BF77j50LzIFNHQ7rcl9 X-Received: by 10.69.31.139 with SMTP id km11mr4529316pbd.163.1388680364686; Thu, 02 Jan 2014 08:32:44 -0800 (PST) Received: from nehalam.linuxnetplumber.net (static-50-53-83-51.bvtn.or.frontiernet.net. [50.53.83.51]) by mx.google.com with ESMTPSA id yz5sm50945376pac.9.2014.01.02.08.32.44 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 02 Jan 2014 08:32:44 -0800 (PST) Date: Thu, 2 Jan 2014 08:32:42 -0800 From: Stephen Hemminger To: Thomas Monjalon Message-ID: <20140102083242.4651a353@nehalam.linuxnetplumber.net> In-Reply-To: <1387582656-1892-1-git-send-email-thomas.monjalon@6wind.com> References: <1387582656-1892-1-git-send-email-thomas.monjalon@6wind.com> X-Mailer: Claws Mail 3.8.1 (GTK+ 2.24.10; x86_64-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Cc: dev@dpdk.org Subject: Re: [dpdk-dev] [PATCH] spinlock: fix atomic and out of order execution X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 02 Jan 2014 16:31:35 -0000 On Sat, 21 Dec 2013 00:37:36 +0100 Thomas Monjalon wrote: > From: Damien Millescamps >=20 > Add lock prefix before xchg instructions in order to be atomic > and flush speculative values to ensure effective execution order > (as an acquire barrier). >=20 > MPLOCKED is a "lock" in multicore case. >=20 > Signed-off-by: Damien Millescamps > Signed-off-by: Thomas Monjalon > --- > lib/librte_eal/common/include/rte_spinlock.h | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) >=20 > diff --git a/lib/librte_eal/common/include/rte_spinlock.h b/lib/librte_ea= l/common/include/rte_spinlock.h > index f7a245a..8edb971 100644 > --- a/lib/librte_eal/common/include/rte_spinlock.h > +++ b/lib/librte_eal/common/include/rte_spinlock.h > @@ -51,6 +51,7 @@ > extern "C" { > #endif > =20 > +#include > #include > #ifdef RTE_FORCE_INTRINSICS > #include > @@ -93,7 +94,7 @@ rte_spinlock_lock(rte_spinlock_t *sl) > int lock_val =3D 1; > asm volatile ( > "1:\n" > - "xchg %[locked], %[lv]\n" > + MPLOCKED "xchg %[locked], %[lv]\n" > "test %[lv], %[lv]\n" > "jz 3f\n" > "2:\n" > @@ -124,7 +125,7 @@ rte_spinlock_unlock (rte_spinlock_t *sl) > #ifndef RTE_FORCE_INTRINSICS > int unlock_val =3D 0; > asm volatile ( > - "xchg %[locked], %[ulv]\n" > + MPLOCKED "xchg %[locked], %[ulv]\n" > : [locked] "=3Dm" (sl->locked), [ulv] "=3Dq" (unlock_val) > : "[ulv]" (unlock_val) > : "memory"); > @@ -148,7 +149,7 @@ rte_spinlock_trylock (rte_spinlock_t *sl) > int lockval =3D 1; > =20 > asm volatile ( > - "xchg %[locked], %[lockval]" > + MPLOCKED "xchg %[locked], %[lockval]" > : [locked] "=3Dm" (sl->locked), [lockval] "=3Dq" (lockval) > : "[lockval]" (lockval) > : "memory"); The locked prefix is required for xchg instruction. The processor does it automatically. http://www.intel.com/content/www/us/en/processors/architectures-software-de= veloper-manuals.html "The XCHG (exchange) instruction swaps the contents of two operands. This i= nstruction takes the place of three MOV instructions and does not require a temporary location to save the cont= ents of one operand location while the other is being loaded. When a memory operand is used with the XCHG instruct= ion, the processor=E2=80=99s LOCK signal is automatically asserted.