From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 7F54E1F5 for ; Tue, 9 Dec 2014 18:45:57 +0100 (CET) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 09 Dec 2014 09:14:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.07,546,1413270000"; d="scan'208";a="644939066" Received: from gklab-18-011.igk.intel.com ([10.102.18.11]) by fmsmga002.fm.intel.com with ESMTP; 09 Dec 2014 09:14:48 -0800 From: miroslaw.walukiewicz@intel.com To: dev@dpdk.org Date: Tue, 09 Dec 2014 12:14:47 -0500 Message-ID: <20141209171447.9954.48212.stgit@gklab-18-011.igk.intel.com> User-Agent: StGit/0.17-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Subject: [dpdk-dev] [PATCH] ixgbe: fix a problem with NIC TSO offload X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 09 Dec 2014 17:45:57 -0000 From: Miroslaw Walukiewicz The patch fixes a minor issue with setting up of TSO feature for ixgbe NICs. The values for l4_len and tso_segsz was chagned first by txoffload mask and next set up in the NIC descriptor. Signed-off-by: Mirek Walukiewicz --- lib/librte_pmd_ixgbe/ixgbe_rxtx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/librte_pmd_ixgbe/ixgbe_rxtx.c b/lib/librte_pmd_ixgbe/ixgbe_rxtx.c index 8559ef6..c9c3104 100644 --- a/lib/librte_pmd_ixgbe/ixgbe_rxtx.c +++ b/lib/librte_pmd_ixgbe/ixgbe_rxtx.c @@ -390,13 +390,13 @@ ixgbe_set_xmit_ctx(struct igb_tx_queue* txq, type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4 | IXGBE_ADVTXD_TUCMD_L4T_TCP | IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT; + mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT; + mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT; tx_offload_mask.l2_len = ~0; tx_offload_mask.l3_len = ~0; tx_offload_mask.l4_len = ~0; tx_offload_mask.tso_segsz = ~0; - mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT; - mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT; } else { /* no TSO, check if hardware checksum is needed */ if (ol_flags & PKT_TX_IP_CKSUM) { type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;