From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f47.google.com (mail-pa0-f47.google.com [209.85.220.47]) by dpdk.org (Postfix) with ESMTP id 441BCAD89 for ; Wed, 4 Feb 2015 00:40:14 +0100 (CET) Received: by mail-pa0-f47.google.com with SMTP id lj1so102280479pab.6 for ; Tue, 03 Feb 2015 15:40:13 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:message-id:in-reply-to :references:mime-version:content-type:content-transfer-encoding; bh=tMgns+8zVfFU4SEVQ1J53bYQA1BKHKNEvfSi/Ut6wOg=; b=DQ6W4DG0zWMuGChI2zgbgDjfOuBkhxhKQgyrL1UeZC+teRwCttcrKfkQptJC8wLG/C M8aBnKeqstITqF7xHFzBXX4y54YjuBH4sX3mTRjZ5oFxe4EbIFyFsg1a5RaZRwqOwv5c XL2btQIfDRKwfaDTNc4daiiQqAN5T+iKvS7yasHFeJRmiy67bGYFhL1VIyy6CwjYLezZ Tcv4kSGImEd8NKGUmI/YpwRKc5i/TI2K4XxAPg3gctZoACU1AQwRJfzTLHwWra/fALnJ eYu29P1YByRA2LrXBO0Mg6EYy3jcBtixRtAfGVaqWesD1WKgmyonTeERuYOA9y3Y4740 DHaQ== X-Gm-Message-State: ALoCoQlSifDBA2bSXXstumQ7Ft60UdK74yENCaJNnbKRfwwICVG2H0uSjpNz6rExKMjpMEA0VO1E X-Received: by 10.70.90.39 with SMTP id bt7mr41213280pdb.52.1423006813480; Tue, 03 Feb 2015 15:40:13 -0800 (PST) Received: from urahara (static-50-53-82-155.bvtn.or.frontiernet.net. [50.53.82.155]) by mx.google.com with ESMTPSA id z1sm3229567pda.78.2015.02.03.15.40.12 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 03 Feb 2015 15:40:13 -0800 (PST) Date: Tue, 3 Feb 2015 15:40:12 -0800 From: Stephen Hemminger To: Zhou Danny Message-ID: <20150203154012.7ef2495a@urahara> In-Reply-To: <1422951511-28143-1-git-send-email-danny.zhou@intel.com> References: <1422951511-28143-1-git-send-email-danny.zhou@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Cc: dev@dpdk.org Subject: Re: [dpdk-dev] [PATCH v2 0/5] Interrupt mode for PMD X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Feb 2015 23:40:14 -0000 On Tue, 3 Feb 2015 16:18:26 +0800 Zhou Danny wrote: > 2) UIO only supports a single interrupt vector which has to been shared by > LSC interrupt and interrupts assigned to dedicated rx queues. UIO uses msi-x and there is no fundamental reason it could not use one IRQ for LSC and one IRQ per queue. Might require some more work in base kernel but not that hard.