From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 71FE5ADC3 for ; Tue, 24 Feb 2015 10:49:47 +0100 (CET) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP; 24 Feb 2015 01:49:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.09,637,1418112000"; d="scan'208";a="670701095" Received: from bricha3-mobl3.ger.corp.intel.com ([10.243.20.32]) by fmsmga001.fm.intel.com with SMTP; 24 Feb 2015 01:49:34 -0800 Received: by (sSMTP sendmail emulation); Tue, 24 Feb 2015 09:49:34 +0025 Date: Tue, 24 Feb 2015 09:49:34 +0000 From: Bruce Richardson To: Vithal S Mohare Message-ID: <20150224094933.GB8416@bricha3-MOBL3> References: <98DB008FA2AC6644B40AD8C766FAB271020CA67F5E@BOREAL.arubanetworks.com> <20150217130131.GA2729@neilslaptop.think-freely.org> <98DB008FA2AC6644B40AD8C766FAB271020CA68463@BOREAL.arubanetworks.com> <20150219124322.GA24069@hmsreliant.think-freely.org> <98DB008FA2AC6644B40AD8C766FAB271020CA6A3BE@BOREAL.arubanetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <98DB008FA2AC6644B40AD8C766FAB271020CA6A3BE@BOREAL.arubanetworks.com> Organization: Intel Shannon Ltd. User-Agent: Mutt/1.5.23 (2014-03-12) Cc: "dev@dpdk.org" Subject: Re: [dpdk-dev] rte_memcpy optimization patch to dpdk ver 1.7 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Feb 2015 09:49:47 -0000 On Tue, Feb 24, 2015 at 04:25:40AM +0000, Vithal S Mohare wrote: > Hi Neil, > > > While most of the newer CPUs supports ssse3, found a I7 not supporting it. So, DPDK can't run these CPUs? Is this restriction acceptable? > > -sh-3.2$ cat /proc/cpuinfo > processor : 0 > vendor_id : GenuineIntel > cpu family : 6 > model : 26 > model name : Intel(R) Core(TM) i7 CPU 920 @ 2.67GHz > stepping : 5 > cpu MHz : 2660.068 > cache size : 8192 KB > physical id : 0 > siblings : 8 > core id : 0 > cpu cores : 4 > apicid : 0 > fpu : yes > fpu_exception : yes > cpuid level : 11 > wp : yes > flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall nx rdtscp lm constant_tsc pni monitor ds_cpl vmx est tm2 cx16 xtpr popcnt lahf_lm > > Thanks, > -Vithal > Hi Vithal, Something doesn't seem right here. The i7-920 should support up to SSE4.2, therefore including ssse3. See: http://ark.intel.com/products/37147/Intel-Core-i7-920-Processor-8M-Cache-2_66-GHz-4_80-GTs-Intel-QPI Regards, /Bruce > -----Original Message----- > From: Neil Horman [mailto:nhorman@tuxdriver.com] > Sent: Thursday, February 19, 2015 6:13 PM > To: Vithal S Mohare > Cc: dev@dpdk.org > Subject: Re: [dpdk-dev] rte_memcpy optimization patch to dpdk ver 1.7 > > On Wed, Feb 18, 2015 at 04:09:25AM +0000, Vithal S Mohare wrote: > > Ok, crash, as expected. So, now dpdk mandates either AVX2 or SSSE2 supported CPUs. OR applications needs to handle it run-time. > > > No, sse3 is the minimum, but I think thats been the case for quite some time now, I think. > > Neil > > > Thanks, > > -Vithal > > > > -----Original Message----- > > From: Neil Horman [mailto:nhorman@tuxdriver.com] > > Sent: Tuesday, February 17, 2015 6:32 PM > > To: Vithal S Mohare > > Cc: dev@dpdk.org > > Subject: Re: [dpdk-dev] rte_memcpy optimization patch to dpdk ver 1.7 > > > > On Tue, Feb 17, 2015 at 08:39:22AM +0000, Vithal S Mohare wrote: > > > Hi, > > > > > > I am trying to use rte_memcpy optimization patch along with dpdk version 1.7. With the patch, while dpdk itself is compiled, applications failed with below error: > > > ------------------------------- > > > include/rte_memcpy.h:629:2: error: implicit declaration of function > > > '_mm_alignr_epi8' [-Werror=implicit-function-declaration] > > > /home/vithals/adu_src/build/x-men_dev/Default/shumway/infra/dpdk/shumway_obj/lib/../include/rte_memcpy.h:629:2: error: incompatible type for argument 2 of '_mm_storeu_si128' > > > ------------------------------- > > > > > > After including -mssse3 flags, compilation (cross compiled for a x86 linux based platform) went through. Now the question is, when this binary is loaded on system that doesn't support SSSE3 instruction set (but just sse2 etc), what would be the behavior? > > > > > A crash. You'll attempt to send an unknown binary instruction into the execution pipeline and the processor will fault. > > > > Neil > > > > > >