From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f52.google.com (mail-pa0-f52.google.com [209.85.220.52]) by dpdk.org (Postfix) with ESMTP id EEBD33237 for ; Wed, 15 Apr 2015 18:38:25 +0200 (CEST) Received: by pabsx10 with SMTP id sx10so56463195pab.3 for ; Wed, 15 Apr 2015 09:38:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:message-id:in-reply-to :references:mime-version:content-type:content-transfer-encoding; bh=lhw7L34shuKkjdvtILJXRavCrsJOkgtCfx1mMQd8h+I=; b=U0oMufBOtuor75QzJBSExGcp2diGDyPit4EF7NXwF/9hpBhWtl8hcp6d7WT4qyHTfQ /OomgDzCrX+c6cXwGmNUcLqeeRFYsr+8r6YfQvhhqDRPC5LXsmwIF0Shx6cQC5CMJ9zl ahVXRdXopMq12uxJxrB80tHOuyr7zxqsdALNtB1QfMubykIkL4JpnaChEbv9/YlbOYpa MJTUGkQfB/I33nlyKg5MAYk0NdhzKBjnnOX39+HgIYSH+2VMTBtiGPweRVZDQ05EtxgZ yAEEEd8K6tMpCG2Xy5+wQ3W4cZQQysNdI7XnymwZ5lWN5abmnayD2wAhzOTK5zKwTOm9 3xyw== X-Gm-Message-State: ALoCoQn/oPfyoBuH1A3bQHdm1VF2mbsXHWMMEfCC8w5oUna/ny+Jeo8bIb24T5rbm65XnFxwREC1 X-Received: by 10.67.4.230 with SMTP id ch6mr48036948pad.137.1429115905398; Wed, 15 Apr 2015 09:38:25 -0700 (PDT) Received: from urahara (static-50-53-82-155.bvtn.or.frontiernet.net. [50.53.82.155]) by mx.google.com with ESMTPSA id np6sm4599573pdb.80.2015.04.15.09.38.24 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 15 Apr 2015 09:38:25 -0700 (PDT) Date: Wed, 15 Apr 2015 09:36:31 -0700 From: Stephen Hemminger To: "Zhou, Danny" Message-ID: <20150415093631.04e61313@urahara> In-Reply-To: <20150415093420.6fc93b76@urahara> References: <20150414180620.03deb8ee@urahara> <20150415093420.6fc93b76@urahara> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Cc: "dev@dpdk.org" Subject: [dpdk-dev] [PATCH 1/2 kernel] uio: add irq control support to uio_pci_generic X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Apr 2015 16:38:26 -0000 The driver already supported INTX interrupts but had no in kernel function to enable and disable them. It is possible for userspace to do this by accessing PCI config directly, but this racy and better handled by same mechanism that already exists in kernel. Signed-off-by: Stephen Hemminger --- Patch against latest 4.0 upstream kernel --- a/drivers/uio/uio_pci_generic.c 2015-04-15 08:50:15.543900681 -0700 +++ b/drivers/uio/uio_pci_generic.c 2015-04-15 09:00:01.658609786 -0700 @@ -53,6 +53,18 @@ static irqreturn_t irqhandler(int irq, s return IRQ_HANDLED; } +static int irqcontrol(struct uio_info *info, s32 irq_on) +{ + struct uio_pci_generic_dev *gdev = to_uio_pci_generic_dev(info); + struct pci_dev *pdev = gdev->pdev; + + pci_cfg_access_lock(pdev); + pci_intx(pdev, irq_on); + pci_cfg_access_unlock(pdev); + + return 0; +} + static int probe(struct pci_dev *pdev, const struct pci_device_id *id) { @@ -89,6 +101,7 @@ static int probe(struct pci_dev *pdev, gdev->info.irq = pdev->irq; gdev->info.irq_flags = IRQF_SHARED; gdev->info.handler = irqhandler; + gdev->info.irqcontrol = irqcontrol; gdev->pdev = pdev; err = uio_register_device(&pdev->dev, &gdev->info);