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From: Bruce Richardson <bruce.richardson@intel.com>
To: Pavel Odintsov <pavel.odintsov@gmail.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>
Subject: Re: [dpdk-dev] Could not achieve wire speed for 40GE with any DPDK version on XL710 NIC's
Date: Wed, 1 Jul 2015 13:59:18 +0100	[thread overview]
Message-ID: <20150701125918.GA6960@bricha3-MOBL3> (raw)
In-Reply-To: <CALgsdbc93MvV+yiHjSKM-cxQ=P+4LvsKqsBfA8Z=0d648t0+Fw@mail.gmail.com>

On Wed, Jul 01, 2015 at 03:44:57PM +0300, Pavel Odintsov wrote:
> Thanks for answer, Vladimir! So we need look for x16 NIC if we want
> achieve 40GE line rate...
> 
Note that this would only apply for your minimal i.e. 64-byte, packet sizes.
Once you go up to larger e.g. 128B packets, your PCI bandwidth requirements
are lower and you can easier achieve line rate.

/Bruce

> On Wed, Jul 1, 2015 at 3:06 PM, Vladimir Medvedkin <medvedkinv@gmail.com> wrote:
> > Hi Pavel,
> >
> > Looks like you ran into pcie bottleneck. So let's calculate xl710 rx only
> > case.
> > Assume we have 32byte descriptors (if we want more offload).
> > DMA makes one pcie transaction with packet payload, one descriptor writeback
> > and one memory request for free descriptors for every 4 packets. For
> > Transaction Layer Packet (TLP) there is 30 bytes overhead (4 PHY + 6 DLL +
> > 16 header + 4 ECRC). So for 1 rx packet dma sends 30 + 64(packet itself) +
> > 30 + 32 (writeback descriptor) + (16 / 4) (read request for new
> > descriptors). Note that we do not take into account PCIe ACK/NACK/FC Update
> > DLLP. So we have 160 bytes per packet. One lane PCIe 3.0 transmits 1 byte in
> > 1 ns, so x8 transmits 8 bytes  in 1 ns. 1 packet transmits in 20 ns.  Thus
> > in theory pcie 3.0 x8 may transfer not more than 50mpps.
> > Correct me if I'm wrong.
> >
> > Regards,
> > Vladimir
> >
> >

  reply	other threads:[~2015-07-01 12:59 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-28 10:34 Pavel Odintsov
2015-06-28 23:35 ` Keunhong Lee
2015-06-29  6:59   ` Pavel Odintsov
2015-06-29 15:06     ` Keunhong Lee
2015-06-29 15:38       ` Andrew Theurer
2015-06-29 15:41         ` Pavel Odintsov
2015-07-01 12:06           ` Vladimir Medvedkin
2015-07-01 12:44             ` Pavel Odintsov
2015-07-01 12:59               ` Bruce Richardson [this message]
2015-07-01 13:05                 ` Pavel Odintsov
2015-07-01 13:40                   ` Vladimir Medvedkin
2015-07-01 14:22                     ` Anuj Kalia
2015-07-01 17:32                       ` Vladimir Medvedkin
2015-07-01 18:01                         ` Anuj Kalia
2015-07-03  8:35                           ` Pavel Odintsov

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