From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from na01-by2-obe.outbound.protection.outlook.com (mail-by2on0100.outbound.protection.outlook.com [207.46.100.100]) by dpdk.org (Postfix) with ESMTP id 93F75FE5 for ; Mon, 2 Nov 2015 06:15:52 +0100 (CET) Received: from BLUPR0701MB1969.namprd07.prod.outlook.com (10.163.121.20) by BLUPR0701MB1956.namprd07.prod.outlook.com (10.163.121.19) with Microsoft SMTP Server (TLS) id 15.1.312.18; Mon, 2 Nov 2015 05:15:51 +0000 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Jerin.Jacob@caviumnetworks.com; Received: from localhost.localdomain (122.167.182.182) by BLUPR0701MB1969.namprd07.prod.outlook.com (10.163.121.20) with Microsoft SMTP Server (TLS) id 15.1.312.18; Mon, 2 Nov 2015 05:15:47 +0000 Date: Mon, 2 Nov 2015 10:45:21 +0530 From: Jerin Jacob To: David Hunt Message-ID: <20151102051519.GA17659@localhost.localdomain> References: <1446212959-19832-1-git-send-email-david.hunt@intel.com> <1446212959-19832-4-git-send-email-david.hunt@intel.com> MIME-Version: 1.0 Content-Type: text/plain; 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IN NO EVENT SHALL THE COPYRIGHT > + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, > + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT > + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, > + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY > + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE > + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > +*/ > + > +#ifndef _RTE_CYCLES_ARM64_H_ > +#define _RTE_CYCLES_ARM64_H_ > + > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +#include "generic/rte_cycles.h" > + > +/** > + * Read the time base register. > + * > + * @return > + * The time base for this lcore. > + */ > +static inline uint64_t > +rte_rdtsc(void) > +{ > + uint64_t tsc; > + > + asm volatile("mrs %0, CNTVCT_EL0" : "=r" (tsc)); > + > +#ifdef RTE_TIMER_MULTIPLIER > + return tsc * RTE_TIMER_MULTIPLIER; > +#else > + return tsc; > +#endif > + > +} > + > +static inline uint64_t > +rte_rdtsc_precise(void) > +{ > + asm volatile("isb sy" :::); IMO, it should be asm volatile("dmb ish" : : : "memory") to represent the data memory barrier(rte_mb()). > + return rte_rdtsc(); > +} > + > +static inline uint64_t > +rte_get_tsc_cycles(void) { return rte_rdtsc(); } > + > +#ifdef __cplusplus > +} > +#endif > + > +#endif /* _RTE_CYCLES_ARM64_H_ */ > -- > 1.9.1 >