From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f52.google.com (mail-pa0-f52.google.com [209.85.220.52]) by dpdk.org (Postfix) with ESMTP id C427C590C for ; Fri, 20 Nov 2015 17:40:52 +0100 (CET) Received: by padhx2 with SMTP id hx2so121169953pad.1 for ; Fri, 20 Nov 2015 08:40:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=networkplumber-org.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; bh=DXQlgOypDP5v/bVhobdya4gqTmRCEPQ4kVlPeYqg0Fc=; b=Z6DB5BjB0KVYWs2eIx8HTbTu2hHR5VAZgnUEZuJvG+lCtRvxybslZqfeI30avxRIS2 CtlanADsUzdwyQBz6QsT9+o7+c/zkNNFZTsdyuWJOjINfCyBUn2C/lGtnvWk2aGDlS8/ nOO1GIcW0/qId1rvuojb9Ul1FF8ug94QQFvmO0d716k+OLEM8P979Y2MBa/E0cRyePmX ZIswHR/ITmVuAWW6mQO6whfh7wfs+Na5Y0Xb+XzHWTaG+0UT9E/cRODuYg28DdzuIPop koxNIPlz3HszrF0dq6jdL5v2o2MX6tyV7nmwa3GWdZNvVRWgA833TOtcNhORDd8MBnkH c2UA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:message-id:in-reply-to :references:mime-version:content-type:content-transfer-encoding; bh=DXQlgOypDP5v/bVhobdya4gqTmRCEPQ4kVlPeYqg0Fc=; b=i0Jz6o+XqJ4vpXI9x4EivwZQKg4IOYkHHd3Db9hmbZ+OsXbFm8qs+orKb/HO2BIxpc TRypGO4X/QZhI0AF5iQk7DABEiQuXiV5G9ff5GQfutxLCkqL4jOfSTuAPUTe0AOPg7mW 4PBk6rslypTByTH3RT/SMx1wC+EdGSp+euzC3EzVSRyYieAR7N2YuXR++1+d2xv/aAaJ 8+p/dhJbEx0dEuYhAIGtxzS/HJZK5737iGQf10kmUVkzSGq1UHXeJij78kXbAR6SBklb 8AxUgDlSKg2YoRx7rlYAd5eofJLfhhCOG24iJRke3MghpeVWqWtotjkdBJDPswV45U71 8lhA== X-Gm-Message-State: ALoCoQkHsv+Of4/dfaeIMstwm7SJ9ZrIQk/SkJiZU5/Fzdu2BsDwkRsI+fFxX3eqkFtzV33EG5/I X-Received: by 10.66.221.105 with SMTP id qd9mr20562469pac.46.1448037652128; Fri, 20 Nov 2015 08:40:52 -0800 (PST) Received: from xeon-e3 (static-50-53-82-155.bvtn.or.frontiernet.net. [50.53.82.155]) by smtp.gmail.com with ESMTPSA id c1sm283785pap.36.2015.11.20.08.40.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 20 Nov 2015 08:40:51 -0800 (PST) Date: Fri, 20 Nov 2015 08:41:02 -0800 From: Stephen Hemminger To: Wenzhuo Lu Message-ID: <20151120084102.561476fd@xeon-e3> In-Reply-To: <1448003879-29960-18-git-send-email-wenzhuo.lu@intel.com> References: <1448003879-29960-1-git-send-email-wenzhuo.lu@intel.com> <1448003879-29960-18-git-send-email-wenzhuo.lu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Cc: dev@dpdk.org Subject: Re: [dpdk-dev] [PATCH 17/17] ixgbe: add new device X550T1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Nov 2015 16:40:53 -0000 On Fri, 20 Nov 2015 15:17:58 +0800 Wenzhuo Lu wrote: > Signed-off-by: Wenzhuo Lu > --- > lib/librte_eal/common/include/rte_pci_dev_ids.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/lib/librte_eal/common/include/rte_pci_dev_ids.h b/lib/librte_eal/common/include/rte_pci_dev_ids.h > index e31b934..d088191 100644 > --- a/lib/librte_eal/common/include/rte_pci_dev_ids.h > +++ b/lib/librte_eal/common/include/rte_pci_dev_ids.h > @@ -433,6 +433,7 @@ RTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_DH89XXCC_SFP) > #define IXGBE_DEV_ID_X550EM_X_10G_T 0x15AD > #define IXGBE_DEV_ID_X550EM_X_1G_T 0x15AE > #define IXGBE_DEV_ID_X550T 0x1563 > +#define IXGBE_DEV_ID_X550T1 0x15D1 > #define IXGBE_DEV_ID_X550EM_X_KX4 0x15AA > #define IXGBE_DEV_ID_X550EM_X_KR 0x15AB > > @@ -483,6 +484,7 @@ RTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_X550EM_X_SFP) > RTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_X550EM_X_10G_T) > RTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_X550EM_X_1G_T) > RTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_X550T) > +RTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_X550T1) > RTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_X550EM_X_KX4) > RTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_X550EM_X_KR) This patch is good, glad to see the base driver keep up with the other Intel driver code bases. Has anyone looked into cleaning up the management of PCI id's in the source base. Putting all the PCI'ids for all DPDK drivers in one file with #ifdef's is really not a scalable long term solution. It needs to be split out into each driver.