From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 1040537A6 for ; Thu, 3 Dec 2015 17:46:30 +0100 (CET) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP; 03 Dec 2015 08:46:29 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,378,1444719600"; d="scan'208";a="853253492" Received: from bricha3-mobl3.ger.corp.intel.com ([10.237.208.61]) by fmsmga001.fm.intel.com with SMTP; 03 Dec 2015 08:46:28 -0800 Received: by (sSMTP sendmail emulation); Thu, 03 Dec 2015 16:46:27 +0025 Date: Thu, 3 Dec 2015 16:46:27 +0000 From: Bruce Richardson To: Stephen Hemminger Message-ID: <20151203164626.GA13272@bricha3-MOBL3> References: <1449134905-28261-1-git-send-email-ian.betts@intel.com> <1449134905-28261-3-git-send-email-ian.betts@intel.com> <20151203083139.32b82334@xeon-e3> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20151203083139.32b82334@xeon-e3> Organization: Intel Shannon Ltd. User-Agent: Mutt/1.5.23 (2014-03-12) Cc: dev@dpdk.org, ibetts Subject: Re: [dpdk-dev] [PATCH v5 2/4] examples: add lthread subsystem for performance-thread X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Dec 2015 16:46:31 -0000 On Thu, Dec 03, 2015 at 08:31:39AM -0800, Stephen Hemminger wrote: > On Thu, 3 Dec 2015 09:28:23 +0000 > ibetts wrote: > > > +/* > > + * Atomically set a value and return the old value > > + */ > > +static inline uint64_t > > +atomic64_xchg(uint64_t *ptr, uint64_t val) __attribute__ ((always_inline)); > > +static inline uint64_t > > +atomic64_xchg(uint64_t *ptr, uint64_t val) > > You don't need a forward declaration for this. > Instead do: > > static inline uint64_t __attribute__((always_inline)) > atomic_xchg64(uint64_t *ptr, uint64_t val) > > Really should be in rte_atomic.h as a primitive > and the assembly macro is missing change to ptr so Gcc might optmize it away. > > Something like this mayb? > > static inline uint64_t __attribute__ ((always_inline)); > rte_atomic64_xchg(uint64_t *ptr, uint64_t val) > { > asm volatile ( > MPLOCKED > "xchgq %[ptr],%[val];" > : [val] "=r" (val) > [ptr] "=m" (*ptr) > : [ptr] "m" (*ptr), > "a" (val) > : "memory"); > > return val; > } Rather than using assembly, I believe the gcc builtin __sync_lock_test_and_set is actually an xchg op, so can be used here. /Bruce