From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id 52D2C2C16 for ; Thu, 21 Apr 2016 15:53:41 +0200 (CEST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP; 21 Apr 2016 06:53:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,512,1455004800"; d="scan'208";a="959825254" Received: from bricha3-mobl3.ger.corp.intel.com ([10.237.220.132]) by orsmga002.jf.intel.com with SMTP; 21 Apr 2016 06:53:31 -0700 Received: by (sSMTP sendmail emulation); Thu, 21 Apr 2016 14:53:30 +0025 Date: Thu, 21 Apr 2016 14:53:30 +0100 From: Bruce Richardson To: "Lu, Wenzhuo" Cc: "Kulasek, TomaszX" , "dev@dpdk.org" , "Zhang, Helin" , "Ananyev, Konstantin" Message-ID: <20160421135330.GB15304@bricha3-MOBL3> References: <1460730779-8200-1-git-send-email-tomaszx.kulasek@intel.com> <6A0DE07E22DDAD4C9103DF62FEBC090903455FBF@shsmsx102.ccr.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <6A0DE07E22DDAD4C9103DF62FEBC090903455FBF@shsmsx102.ccr.corp.intel.com> Organization: Intel Shannon Ltd. User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [dpdk-dev] [PATCH] ixgbe: fix bad shift operation in ixgbe_set_pool_tx X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Apr 2016 13:53:41 -0000 On Mon, Apr 18, 2016 at 01:58:02AM +0000, Lu, Wenzhuo wrote: > Hi, > > > -----Original Message----- > > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Tomasz Kulasek > > Sent: Friday, April 15, 2016 10:33 PM > > To: dev@dpdk.org > > Cc: Zhang, Helin; Ananyev, Konstantin > > Subject: [dpdk-dev] [PATCH] ixgbe: fix bad shift operation in ixgbe_set_pool_tx > > > > CID 13190 (#1 of 1): Bad bit shift operation (BAD_SHIFT) > > large_shift: In expression 1 << pool, left shifting by more than 31 bits has > > undefined behavior. The shift amount, pool, is at least 32. > > > > This patch limits mask shift to be in range of 32 bit PFVFTE[1] register, for pool > > > 31. > > > > Fixes: fe3a45fd4104 ("ixgbe: add VMDq support") > > > > Signed-off-by: Tomasz Kulasek > Acked-by: Wenzhuo Lu > As with the rx function, I feel that this isn't the best fix, but that parameter checking and returning an error might be better. Also, since this is the same issue with the same fix repeated for both RX and TX both fixes can probably be included in the same patch for a V2. /Bruce