From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 0B72A5582 for ; Fri, 18 Nov 2016 16:00:48 +0100 (CET) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP; 18 Nov 2016 07:00:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,510,1473145200"; d="scan'208";a="1087128443" Received: from bricha3-mobl3.ger.corp.intel.com ([10.237.221.64]) by fmsmga002.fm.intel.com with SMTP; 18 Nov 2016 07:00:45 -0800 Received: by (sSMTP sendmail emulation); Fri, 18 Nov 2016 15:00:44 +0000 Date: Fri, 18 Nov 2016 15:00:44 +0000 From: Bruce Richardson To: Satha Rao Cc: helin.zhang@intel.com, jingjing.wu@intel.com, jerin.jacob@caviumnetworks.com, jianbo.liu@linaro.org, dev@dpdk.org Message-ID: <20161118150044.GB118060@bricha3-MOBL3.ger.corp.intel.com> References: <1479473533-9393-1-git-send-email-skoteshwar@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1479473533-9393-1-git-send-email-skoteshwar@caviumnetworks.com> Organization: Intel Research and =?iso-8859-1?Q?De=ACvel?= =?iso-8859-1?Q?opment?= Ireland Ltd. User-Agent: Mutt/1.7.1 (2016-10-04) Subject: Re: [dpdk-dev] [PATCH v2] i40e: Fix eth_i40e_dev_init sequence on ThunderX X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 18 Nov 2016 15:00:49 -0000 On Fri, Nov 18, 2016 at 04:52:13AM -0800, Satha Rao wrote: > i40e_asq_send_command: rd32 & wr32 under ThunderX gives unpredictable > results. To solve this include rte memory barriers > > Signed-off-by: Satha Rao > --- > drivers/net/i40e/base/i40e_osdep.h | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/net/i40e/base/i40e_osdep.h b/drivers/net/i40e/base/i40e_osdep.h > index 38e7ba5..ffa3160 100644 > --- a/drivers/net/i40e/base/i40e_osdep.h > +++ b/drivers/net/i40e/base/i40e_osdep.h > @@ -158,7 +158,13 @@ do { \ > ((volatile uint32_t *)((char *)(a)->hw_addr + (reg))) > static inline uint32_t i40e_read_addr(volatile void *addr) > { > +#if defined(RTE_ARCH_ARM64) > + uint32_t val = rte_le_to_cpu_32(I40E_PCI_REG(addr)); > + rte_rmb(); > + return val; > +#else > return rte_le_to_cpu_32(I40E_PCI_REG(addr)); > +#endif > } > #define I40E_PCI_REG_WRITE(reg, value) \ > do { I40E_PCI_REG((reg)) = rte_cpu_to_le_32(value); } while (0) > @@ -171,8 +177,16 @@ static inline uint32_t i40e_read_addr(volatile void *addr) > I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), (reg)), (value)) > > #define rd32(a, reg) i40e_read_addr(I40E_PCI_REG_ADDR((a), (reg))) > +#if defined(RTE_ARCH_ARM64) > +#define wr32(a, reg, value) \ > + do { \ > + I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((a), (reg)), (value)); \ > + rte_wmb(); \ > + } while (0) > +#else > #define wr32(a, reg, value) \ > I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((a), (reg)), (value)) > +#endif > #define flush(a) i40e_read_addr(I40E_PCI_REG_ADDR((a), (I40E_GLGEN_STAT))) > > #define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0])) > -- Would rte_smp_*mb() functions allow you to get a similar result without the need for #ifdefs? It should be a full barrier on weakly ordered platforms which just a compiler barrier on IA. /Bruce