From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id 548262FDD for ; Tue, 22 Nov 2016 14:46:59 +0100 (CET) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP; 22 Nov 2016 05:46:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,533,1473145200"; d="scan'208";a="1088913754" Received: from bricha3-mobl3.ger.corp.intel.com ([10.237.221.64]) by fmsmga002.fm.intel.com with SMTP; 22 Nov 2016 05:46:55 -0800 Received: by (sSMTP sendmail emulation); Tue, 22 Nov 2016 13:46:54 +0000 Date: Tue, 22 Nov 2016 13:46:54 +0000 From: Bruce Richardson To: Jerin Jacob Cc: "Ananyev, Konstantin" , Satha Rao , "Zhang, Helin" , "Wu, Jingjing" , "jianbo.liu@linaro.org" , "dev@dpdk.org" Message-ID: <20161122134654.GA58712@bricha3-MOBL3.ger.corp.intel.com> References: <1479473533-9393-1-git-send-email-skoteshwar@caviumnetworks.com> <2601191342CEEE43887BDE71AB9772583F0DE265@irsmsx105.ger.corp.intel.com> <20161121221638.GA17380@svelivela-lt.caveonetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20161121221638.GA17380@svelivela-lt.caveonetworks.com> Organization: Intel Research and =?iso-8859-1?Q?De=ACvel?= =?iso-8859-1?Q?opment?= Ireland Ltd. User-Agent: Mutt/1.7.1 (2016-10-04) Subject: Re: [dpdk-dev] [PATCH v2] i40e: Fix eth_i40e_dev_init sequence on ThunderX X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Nov 2016 13:47:00 -0000 On Tue, Nov 22, 2016 at 03:46:38AM +0530, Jerin Jacob wrote: > On Sun, Nov 20, 2016 at 11:21:43PM +0000, Ananyev, Konstantin wrote: > > Hi > > > > > > i40e_asq_send_command: rd32 & wr32 under ThunderX gives unpredictable > > > results. To solve this include rte memory barriers > > > > > > Signed-off-by: Satha Rao > > > --- > > > drivers/net/i40e/base/i40e_osdep.h | 14 ++++++++++++++ > > > 1 file changed, 14 insertions(+) > > > > > > diff --git a/drivers/net/i40e/base/i40e_osdep.h b/drivers/net/i40e/base/i40e_osdep.h > > > index 38e7ba5..ffa3160 100644 > > > --- a/drivers/net/i40e/base/i40e_osdep.h > > > +++ b/drivers/net/i40e/base/i40e_osdep.h > > > @@ -158,7 +158,13 @@ do { \ > > > ((volatile uint32_t *)((char *)(a)->hw_addr + (reg))) > > > static inline uint32_t i40e_read_addr(volatile void *addr) > > > { > > > +#if defined(RTE_ARCH_ARM64) > > > + uint32_t val = rte_le_to_cpu_32(I40E_PCI_REG(addr)); > > > + rte_rmb(); > > > + return val; > > > > If you really need an rmb/wmb with MMIO read/writes on ARM, > > I think you can avoid #ifdefs here and use rte_smp_rmb/rte_smp_wmb. > > BTW, I suppose if you need it for i40e, you would need it for other devices too. > > Yes. ARM would need for all devices(typically, the devices on external PCI bus). > I guess rte_smp_rmb may not be the correct abstraction. So we need more of > rte_rmb() as we need only non smp variant on IO side. I guess then it make sense to > create new abstraction in eal with following variants so that each arch > gets opportunity to make what it makes sense that specific platform > > rte_readb_relaxed > rte_readw_relaxed > rte_readl_relaxed > rte_readq_relaxed > rte_writeb_relaxed > rte_writew_relaxed > rte_writel_relaxed > rte_writeq_relaxed > rte_readb > rte_readw > rte_readl > rte_readq > rte_writeb > rte_writew > rte_writel > rte_writeq > > Thoughts ? > That seems like a lot of API calls! Perhaps you can clarify - why would the rte_smp_rmb() not work for you? /Bruce