From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM01-SN1-obe.outbound.protection.outlook.com (mail-sn1nam01on0063.outbound.protection.outlook.com [104.47.32.63]) by dpdk.org (Postfix) with ESMTP id B56C03DC for ; Fri, 16 Dec 2016 11:26:17 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=qjDEynTci+F+1qmaIkkqUiXvYTAxmzlKsO0hRYYYEIc=; b=ARB/7rFyT5yQJxvgRaOdsZFO6xgKqi7GIssjMTe+Rr+AX1Nyj7ZoFH+dJOS7B8hNlOEXQVKZMqbkuyl+6lxIrLsehATn+pLWSGGyT7eww5b04pBBpS4iEmSrD4tOHs5ZzUZ9KhUFdqsKFJKF0Kx9Nj2h7MIIdWfDqs1o5vUBtBw= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Jerin.Jacob@cavium.com; Received: from localhost.localdomain (122.166.153.127) by CY1PR0701MB1725.namprd07.prod.outlook.com (10.163.21.14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.693.12; Fri, 16 Dec 2016 10:26:13 +0000 Date: Fri, 16 Dec 2016 15:55:53 +0530 From: Jerin Jacob To: Jianbo Liu CC: , "Ananyev, Konstantin" , Thomas Monjalon , Bruce Richardson , Jan Viktorin Message-ID: <20161216102551.GA10515@localhost.localdomain> References: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com> <1481680558-4003-14-git-send-email-jerin.jacob@caviumnetworks.com> <20161215100423.GA6712@localhost.localdomain> <20161215110807.GA10881@localhost.localdomain> MIME-Version: 1.0 Content-Type: text/plain; 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CY1PR0701MB1725; 6:pFhDkq58k3zycTN8PsOkHhHdtEHj9DD1mgsnZUofgUub/Nenear6WE/FT0Gp2yUdNH6AHxa1H4fz8unOPUgjX08Z6CabqQguSrhskf221M8cUDo899tZr8wBEsxrPzsNJrICZQLOAel7JdE61SE4QtFPBN54uYtpGfdrnE7SZY8V4Zsjh+ulxtDsRThAy2ICebl3vhRo6Asy+RgS6tujAIIpz6jABj1WIvCdZzXD/WXInetxvYIztWnChYEoLShoTiDKcxbjEldEStYSPQ2Wu4n3/gmdpVV6cYyzQgMiAT2gUz391WHXbBYgGpQzTIVl; 5:b1d2hW90fmd7T82BJ4WYgBCRrlJvPIMV8INgnmqPLZ/rW9VfV4EbJm8qXlcMUErU0QAcaggTlN1CI3ma6ssyjT3KT1b7r9/XWutMWccoEIIOw0Ey+ZM+PKxIwNeHYGswN51E1tlXy7IHlh71GoqnGg==; 24:2moAPaBZeRv+in3VPYfnhw1xnYhNVt6KCRdBZKTyDuVcwCFJCZg3yWXCj1qFbN8XFeXsLygP1f9goNZXUpl3P/4/3Ai0V+dtheZHbdy7LLw= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; CY1PR0701MB1725; 7:qXtXWiMJakmR6ZMYfKSA1UDSShWv/nvB+M0fOqJTrVjre6HG3ZRhaN8LQB7sGTU5SPEiOB7cl3uN6Vn+GiBmJZkIkZnCcYH9iv5rX6/PUYDlU6pVgsOWUHjk5Qq2FVmjewuVYLGLIRVBLXrEpGpz0ic8voktLPGJSuZIjUciTtnuDSq/8mXphqfDKa4eJgF+K0jvH7f4y/+UmfXR+S1E3PvOpDRqGbtT5hS1SfptWSsJW2UnNm5U13cb4PqcHw//AYUXfph+VLdi2HIVz3crz3y4E69TWlu5PGJCjoXi+ROMCYBlCEr0qsmBG2C3DzPpJWy13ndR672e/lh/E1/10GB643KXwS4TsL43JA6zzbw= X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Dec 2016 10:26:13.1705 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR0701MB1725 Subject: Re: [dpdk-dev] [PATCH 13/28] eal/arm64: override I/O device read/write access for arm64 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Dec 2016 10:26:18 -0000 On Fri, Dec 16, 2016 at 06:12:13PM +0800, Jianbo Liu wrote: > On 15 December 2016 at 19:08, Jerin Jacob > wrote: > > On Thu, Dec 15, 2016 at 06:17:32PM +0800, Jianbo Liu wrote: > >> On 15 December 2016 at 18:04, Jerin Jacob > >> wrote: > >> > On Thu, Dec 15, 2016 at 05:53:05PM +0800, Jianbo Liu wrote: > >> >> On 14 December 2016 at 09:55, Jerin Jacob > >> >> wrote: > >> >> > Override the generic I/O device memory read/write access and implement it > >> >> > using armv8 instructions for arm64. > >> >> > > >> >> > Signed-off-by: Jerin Jacob > >> >> > --- > >> >> > lib/librte_eal/common/include/arch/arm/rte_io.h | 4 + > >> >> > lib/librte_eal/common/include/arch/arm/rte_io_64.h | 183 +++++++++++++++++++++ > >> >> > 2 files changed, 187 insertions(+) > >> >> > create mode 100644 lib/librte_eal/common/include/arch/arm/rte_io_64.h > >> >> > > >> >> > diff --git a/lib/librte_eal/common/include/arch/arm/rte_io.h b/lib/librte_eal/common/include/arch/arm/rte_io.h > >> >> > index 74c1f2c..9593b42 100644 > >> >> > --- a/lib/librte_eal/common/include/arch/arm/rte_io.h > >> >> > +++ b/lib/librte_eal/common/include/arch/arm/rte_io.h > >> >> > @@ -38,7 +38,11 @@ > >> >> > extern "C" { > >> >> > #endif > >> >> > > >> >> > +#ifdef RTE_ARCH_64 > >> >> > +#include "rte_io_64.h" > >> >> > +#else > >> >> > #include "generic/rte_io.h" > >> >> > +#endif > >> >> > > >> >> > #ifdef __cplusplus > >> >> > } > >> >> > diff --git a/lib/librte_eal/common/include/arch/arm/rte_io_64.h b/lib/librte_eal/common/include/arch/arm/rte_io_64.h > >> >> > new file mode 100644 > >> >> > index 0000000..09e7a89 > >> >> > --- /dev/null > >> >> > +++ b/lib/librte_eal/common/include/arch/arm/rte_io_64.h > >> >> > @@ -0,0 +1,183 @@ > >> >> > +/* > >> >> > + * BSD LICENSE > >> >> > + * > >> >> > + * Copyright (C) Cavium networks Ltd. 2016. > >> >> > + * > >> >> > + * Redistribution and use in source and binary forms, with or without > >> >> > + * modification, are permitted provided that the following conditions > >> >> > + * are met: > >> >> > + * > >> >> > + * * Redistributions of source code must retain the above copyright > >> >> > + * notice, this list of conditions and the following disclaimer. > >> >> > + * * Redistributions in binary form must reproduce the above copyright > >> >> > + * notice, this list of conditions and the following disclaimer in > >> >> > + * the documentation and/or other materials provided with the > >> >> > + * distribution. > >> >> > + * * Neither the name of Cavium networks nor the names of its > >> >> > + * contributors may be used to endorse or promote products derived > >> >> > + * from this software without specific prior written permission. > >> >> > + * > >> >> > + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS > >> >> > + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT > >> >> > + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR > >> >> > + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT > >> >> > + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, > >> >> > + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT > >> >> > + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, > >> >> > + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY > >> >> > + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > >> >> > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE > >> >> > + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > >> >> > + */ > >> >> > + > >> >> > +#ifndef _RTE_IO_ARM64_H_ > >> >> > +#define _RTE_IO_ARM64_H_ > >> >> > + > >> >> > +#ifdef __cplusplus > >> >> > +extern "C" { > >> >> > +#endif > >> >> > + > >> >> > +#include > >> >> > + > >> >> > +#define RTE_OVERRIDE_IO_H > >> >> > + > >> >> > +#include "generic/rte_io.h" > >> >> > +#include "rte_atomic_64.h" > >> >> > + > >> >> > +static inline __attribute__((always_inline)) uint8_t > >> >> > +__rte_arm64_readb(const volatile void *addr) > >> >> > +{ > >> >> > + uint8_t val; > >> >> > + > >> >> > + asm volatile( > >> >> > + "ldrb %w[val], [%x[addr]]" > >> >> > + : [val] "=r" (val) > >> >> > + : [addr] "r" (addr)); > >> >> > + return val; > >> >> > +} > >> >> > + > >> >> > +static inline __attribute__((always_inline)) uint16_t > >> >> > +__rte_arm64_readw(const volatile void *addr) > >> >> > +{ > >> >> > + uint16_t val; > >> >> > + > >> >> > + asm volatile( > >> >> > + "ldrh %w[val], [%x[addr]]" > >> >> > + : [val] "=r" (val) > >> >> > + : [addr] "r" (addr)); > >> >> > + return val; > >> >> > +} > >> >> > + > >> >> > +static inline __attribute__((always_inline)) uint32_t > >> >> > +__rte_arm64_readl(const volatile void *addr) > >> >> > +{ > >> >> > + uint32_t val; > >> >> > + > >> >> > + asm volatile( > >> >> > + "ldr %w[val], [%x[addr]]" > >> >> > + : [val] "=r" (val) > >> >> > + : [addr] "r" (addr)); > >> >> > + return val; > >> >> > +} > >> >> > + > >> >> > +static inline __attribute__((always_inline)) uint64_t > >> >> > +__rte_arm64_readq(const volatile void *addr) > >> >> > +{ > >> >> > + uint64_t val; > >> >> > + > >> >> > + asm volatile( > >> >> > + "ldr %x[val], [%x[addr]]" > >> >> > + : [val] "=r" (val) > >> >> > + : [addr] "r" (addr)); > >> >> > + return val; > >> >> > +} > >> >> > + > >> >> > +static inline __attribute__((always_inline)) void > >> >> > +__rte_arm64_writeb(uint8_t val, volatile void *addr) > >> >> > +{ > >> >> > + asm volatile( > >> >> > + "strb %w[val], [%x[addr]]" > >> >> > + : > >> >> > + : [val] "r" (val), [addr] "r" (addr)); > >> >> > +} > >> >> > + > >> >> > +static inline __attribute__((always_inline)) void > >> >> > +__rte_arm64_writew(uint16_t val, volatile void *addr) > >> >> > +{ > >> >> > + asm volatile( > >> >> > + "strh %w[val], [%x[addr]]" > >> >> > + : > >> >> > + : [val] "r" (val), [addr] "r" (addr)); > >> >> > +} > >> >> > + > >> >> > +static inline __attribute__((always_inline)) void > >> >> > +__rte_arm64_writel(uint32_t val, volatile void *addr) > >> >> > +{ > >> >> > + asm volatile( > >> >> > + "str %w[val], [%x[addr]]" > >> >> > + : > >> >> > + : [val] "r" (val), [addr] "r" (addr)); > >> >> > +} > >> >> > + > >> >> > +static inline __attribute__((always_inline)) void > >> >> > +__rte_arm64_writeq(uint64_t val, volatile void *addr) > >> >> > +{ > >> >> > + asm volatile( > >> >> > + "str %x[val], [%x[addr]]" > >> >> > + : > >> >> > + : [val] "r" (val), [addr] "r" (addr)); > >> >> > +} > >> >> > >> >> I'm not quite sure about these overridings. Can you explain the > >> >> benefit to do so? > >> > > >> > Better to be native if there is option. That all. Do you see any issue? > >> > or what is the real concern? > >> > > >> > >> I think it's the same as the generic c version after compiling. Am I right? > > > > I really don't that is the case for all the scenarios like compiler may > > combine two 16bit reads one 32bit read etc and which will impact on IO > > I wonder which compiler will do that as armv8 is 32/64 bit system? Not specific to armv8. Two consecutive continues 16bits reads one 32bit read for optimization. Any idea why Linux kernel doing explicit instructions for readl/writel? obviously not for fun. > > > register access. > > > > But, I am sure the proposed scheme generates correct instruction in all the cases.