From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf0-f181.google.com (mail-pf0-f181.google.com [209.85.192.181]) by dpdk.org (Postfix) with ESMTP id D916CFBC5 for ; Tue, 20 Dec 2016 18:11:59 +0100 (CET) Received: by mail-pf0-f181.google.com with SMTP id 189so30007122pfz.3 for ; Tue, 20 Dec 2016 09:11:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=networkplumber-org.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=I/tmPm67pXy0Y4Lzf5yVFkVH6+VpLTeUd19BXVLgeuQ=; b=o/sQ8hc2JxaSzsTBugi0ZV31pADfIKJQ845xLcE3aFFUPqO7EblCPpaEpk848qxRes M7Hw6QdUGokw29c9eZEW2NO9fmss6G9wGGqyktKxhf+OvWtJNs+ozyJs5jEN+p8QTIYL 6TiIKSmALZkcm1CBI9bJLeZ/BTvSF93tHu061/fNzCZmA8b1CxeUdAjgWudSLwGLB/mh YmKhPbxx88fuOjlJcbrW3l8gKDrIuj7U6cFTvyuLrOnapajQ8i7JuYE6fvrV+DtLvodR akZC6yaU6ZCd69JeZu8JxYTtiBl3l510Da1GKgaZpRySEwzF93Akr0mJDxPrEFTqBiBz yjtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=I/tmPm67pXy0Y4Lzf5yVFkVH6+VpLTeUd19BXVLgeuQ=; b=mW3ZzvI+OizpVTto0Gy/BdC88bRpgRPR8S5GzHQ5Fx5JhnP2r/F2xNlTVW6dQsw5r6 U7Lns7qElDQHixKjaTqhDmIFihIuUr4zOGj6q43iwmcvvV4PXkb/jIVWSQU8T+IKLtPw OizMW9ghlwttTrIk+It6NNcseGRT3VqXa5bOCZr7NQkugYKqcWc6BNFiFtT3tWNUSMTi h3XW6ujYYqAmdri2vdvv942apdeBWM1xYpBet2RyqwPsZ5gvW7eNtxs11P0QZfVMzDxJ bKNLJNAGmPAIW+3PL8KkVDXRKZd3b1uGLzdg/nnxN8DMH/3OV952BGfp8lZXzqGAdVJf w0MA== X-Gm-Message-State: AIkVDXKhUlIoidLso8m/9fz7hruIFdLT6YMBIa6FMWHWQ+YigliShspc/1JSirJr4GpsCw== X-Received: by 10.84.213.150 with SMTP id g22mr598207pli.11.1482253919127; Tue, 20 Dec 2016 09:11:59 -0800 (PST) Received: from xeon-e3 (204-195-18-65.wavecable.com. [204.195.18.65]) by smtp.gmail.com with ESMTPSA id z29sm14125501pgc.11.2016.12.20.09.11.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 20 Dec 2016 09:11:58 -0800 (PST) Date: Tue, 20 Dec 2016 09:11:56 -0800 From: Stephen Hemminger To: Jan Blunck Cc: Shreyansh Jain , dev@dpdk.org, David Marchand , Thomas Monjalon , Ferruh Yigit , jianbo.liu@linaro.org Message-ID: <20161220091156.4442cb07@xeon-e3> In-Reply-To: References: <1481636232-2300-1-git-send-email-shreyansh.jain@nxp.com> <1481893853-31790-1-git-send-email-shreyansh.jain@nxp.com> <1481893853-31790-3-git-send-email-shreyansh.jain@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: [dpdk-dev] [PATCH v3 02/12] eal/bus: introduce bus abstraction X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 20 Dec 2016 17:12:00 -0000 On Tue, 20 Dec 2016 14:17:14 +0100 Jan Blunck wrote: > On Fri, Dec 16, 2016 at 2:10 PM, Shreyansh Jain wrote: > > This patch introduces the rte_bus abstraction for devices and drivers in > > EAL framework. The model is: > > - One or more buses are connected to a CPU (or core) > > - One or more devices are conneted to a Bus > > - Drivers are running instances which manage one or more devices > > - Bus is responsible for identifying devices (and interrupt propogation) > > - Driver is responsible for initializing the device > > > > This patch adds a 'rte_bus' class which rte_driver and rte_device refer. > > This way, each device (rte_xxx_device) would have reference to the bus > > it is based on. As well as, each driver (rte_xxx_driver) would have link > > to the bus and devices on it for servicing. > > > > __ rte_bus_list > > / > > +----------'---+ > > |rte_bus | > > | driver_list------> List of rte_bus specific > > | device_list---- devices > > | | `-> List of rte_bus associated > > | | drivers > > +--|------|----+ > > _________/ \_________ > > +--------/----+ +-\---------------+ > > |rte_device | |rte_driver | > > | rte_bus | | rte_bus | > > | rte_driver | | ... | > > | ... | +---------...-----+ > > | | ||| > > +---||--------+ ||| > > || ||| > > | \ \\\ > > | \_____________ \\\ > > | \ ||| > > +------|---------+ +----|----------+ ||| > > |rte_pci_device | |rte_xxx_device | ||| > > | .... | | .... | ||| > > +----------------+ +---------------+ / | \ > > / | \ > > _____________________/ / \ > > / ___/ \ > > +-------------'--+ +------------'---+ +--'------------+ > > |rte_pci_driver | |rte_vdev_driver | |rte_xxx_driver | > > | .... | | .... | | .... | > > +----------------+ +----------------+ +---------------+ > > > > This patch only enables the bus references on rte_driver and rte_driver. > > EAL wide global device and driver list continue to exist until an instance > > of bus is added in subsequent patches. > > > > This patch also introduces RTE_REGISTER_BUS macro on the lines of > > RTE_PMD_REGISTER_XXX. Key difference is that the constructor priority has > > been explicitly set to 101 so as to execute bus registration before PMD. > > > > Signed-off-by: Shreyansh Jain > > Ok, but let's keep this as bus type not bus. It gets really hard and complex to enumerate all layers of PCI bus and bridges.