From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-f175.google.com (mail-wr0-f175.google.com [209.85.128.175]) by dpdk.org (Postfix) with ESMTP id DE0E42B94 for ; Thu, 2 Mar 2017 08:56:46 +0100 (CET) Received: by mail-wr0-f175.google.com with SMTP id l37so46020305wrc.1 for ; Wed, 01 Mar 2017 23:56:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to :user-agent; bh=vAeaxZpYkuEiwUIVDjDglEofawUJAmA/V1v5IXwOZGs=; b=QBJJhyYKgGNjz0tjiQ+E3Pq+Zces8EEpUFZinm4gyCwcFYQ7Ygz75NatXLKIDgeCUJ ZjrByvJ6Bcmy43TCcvM/ix2nxILND8aCvkWUs64Cs6Af0JZzBJrxTQTWdaw1KfIQ8fGY +WA7+C2xG9rRHtoA28PfHvfJ/7BNSV6Z5v68ojOLynsMUs/VQViLOdm1TL1iQ5NCswJU ZfGKrd4X4DTNWFidpfBycgxOexaC0LTHAtwSslBRBrJgJL/KcLye9PunIXEwWDPRczqf aXOONBeIvgzI6dZM8VvN2s7Qls4OuLP+MrexUOXijwMb3MBo9HLo+sYAjaFbVRd2sIl3 RxaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to:user-agent; bh=vAeaxZpYkuEiwUIVDjDglEofawUJAmA/V1v5IXwOZGs=; b=WYVyGH1sQTULgu0dDVr6MHC2UzP/tpZMhGHCkT9nEL0+8iakaidL+9KkwHUbpsrtO6 0wJzwdwEgK2yHRQYRzpqifX7uDsiBRYXY5onkBUT9eErgCYQL9W1q44Ozn4Qb1gX3I07 yBZ3SdfSAjV0PrbdS7kB5NsgW+4/7LOKNxDBXpMCbeAuXF+pCD9cscUbgfzQTna5da7y 5BEf5LwnNy/oMdF5b17ADB2/ubsIB7ZTkVPNeowlMrVHibqkr4d86uhRXLDNjrlt7rD9 WR4ylk9Tri6WU1Z9lL5rWpX7mbZBbTfHJZcQMkZ2EEp7bQbPN3kwxLoVFgV2SA0H52IA VUWg== X-Gm-Message-State: AMke39mC9BMumJwCP6S5qocT/73d49pvqgQRdpLhRLdLt3TLCuaGYbd4OgteNsULEF9x0fFs X-Received: by 10.223.165.17 with SMTP id i17mr12167096wrb.62.1488441406423; Wed, 01 Mar 2017 23:56:46 -0800 (PST) Received: from autoinstall.dev.6wind.com (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id l45sm9727518wrc.14.2017.03.01.23.56.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 01 Mar 2017 23:56:45 -0800 (PST) Date: Thu, 2 Mar 2017 08:56:37 +0100 From: =?iso-8859-1?Q?N=E9lio?= Laranjeiro To: Olivier Matz Cc: dev@dpdk.org, thomas.monjalon@6wind.com, konstantin.ananyev@intel.com, wenzhuo.lu@intel.com, helin.zhang@intel.com, jingjing.wu@intel.com, adrien.mazarguil@6wind.com, ferruh.yigit@intel.com, bruce.richardson@intel.com Message-ID: <20170302075637.GA22756@autoinstall.dev.6wind.com> References: <1479981261-19512-1-git-send-email-olivier.matz@6wind.com> <1488388752-1819-1-git-send-email-olivier.matz@6wind.com> <1488388752-1819-6-git-send-email-olivier.matz@6wind.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1488388752-1819-6-git-send-email-olivier.matz@6wind.com> User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [dpdk-dev] [PATCH 5/6] net/mlx5: implement descriptor status API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 02 Mar 2017 07:56:47 -0000 Hi Olivier, On Wed, Mar 01, 2017 at 06:19:11PM +0100, Olivier Matz wrote: > Since there is no "descriptor done" flag like on Intel drivers, the > approach is different on mlx5 driver. > - for Tx, we call txq_complete() to free descriptors processed by > the hw, then we check if the descriptor is between tail and head > - for Rx, we need to browse the cqes, managing compressed ones, > to get the number of used descriptors. > > Signed-off-by: Olivier Matz > --- > drivers/net/mlx5/mlx5.c | 2 ++ > drivers/net/mlx5/mlx5_rxtx.c | 83 ++++++++++++++++++++++++++++++++++++++++++++ > drivers/net/mlx5/mlx5_rxtx.h | 2 ++ > 3 files changed, 87 insertions(+) > > diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c > index d4bd469..4a6450c 100644 > --- a/drivers/net/mlx5/mlx5.c > +++ b/drivers/net/mlx5/mlx5.c > @@ -222,6 +222,8 @@ static const struct eth_dev_ops mlx5_dev_ops = { > .rss_hash_update = mlx5_rss_hash_update, > .rss_hash_conf_get = mlx5_rss_hash_conf_get, > .filter_ctrl = mlx5_dev_filter_ctrl, > + .rx_descriptor_status = mlx5_rx_descriptor_status, > + .tx_descriptor_status = mlx5_tx_descriptor_status, > }; > > static struct { > diff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c > index 88b0354..b3375f6 100644 > --- a/drivers/net/mlx5/mlx5_rxtx.c > +++ b/drivers/net/mlx5/mlx5_rxtx.c > @@ -345,6 +345,89 @@ mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe) > } > > /** > + * DPDK callback to check the status of a tx descriptor. > + * > + * @param dev > + * Pointer to Ethernet device structure. > + * @param[in] tx_queue_id > + * The identifier of the tx queue. > + * @param[in] offset > + * The index of the descriptor in the ring. > + * > + * @return > + * The status of the tx descriptor. > + */ > +int > +mlx5_tx_descriptor_status(struct rte_eth_dev *dev, uint16_t tx_queue_id, > + uint16_t offset) > +{ > + struct txq *txq = dev->data->tx_queues[tx_queue_id]; > + const unsigned int elts_n = 1 << txq->elts_n; > + const unsigned int elts_cnt = elts_n - 1; > + unsigned int used; > + > + txq_complete(txq); > + If you submit a v2 please remove this empty line. > + used = (txq->elts_head - txq->elts_tail) & elts_cnt; > + if (offset < used) > + return RTE_ETH_TX_DESC_FULL; > + return RTE_ETH_TX_DESC_DONE; > +} > + > +/** > + * DPDK callback to check the status of a rx descriptor. > + * > + * @param dev > + * Pointer to Ethernet device structure. > + * @param[in] tx_queue_id > + * The identifier of the rx queue. > + * @param[in] offset > + * The index of the descriptor in the ring. > + * > + * @return > + * The status of the rx descriptor. > + */ > +int > +mlx5_rx_descriptor_status(struct rte_eth_dev *dev, uint16_t rx_queue_id, > + uint16_t offset) > +{ > + struct rxq *rxq = dev->data->rx_queues[rx_queue_id]; > + struct rxq_zip *zip = &rxq->zip; > + volatile struct mlx5_cqe *cqe; > + const unsigned int cqe_n = (1 << rxq->cqe_n); > + const unsigned int cqe_cnt = cqe_n - 1; > + unsigned int cq_ci; > + unsigned int used; > + > + /* if we are processing a compressed cqe */ > + if (zip->ai) { > + used = zip->cqe_cnt - zip->ca; > + cq_ci = zip->cq_ci; > + } else { > + used = 0; > + cq_ci = rxq->cq_ci; > + } > + cqe = &(*rxq->cqes)[cq_ci & cqe_cnt]; > + while (check_cqe(cqe, cqe_n, cq_ci) == 0) { > + int8_t op_own; > + unsigned int n; > + > + op_own = cqe->op_own; > + if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) > + n = ntohl(cqe->byte_cnt); > + else > + n = 1; > + cq_ci += n; > + used += n; > + cqe = &(*rxq->cqes)[cq_ci & cqe_cnt]; > + } > + used = RTE_MIN(used, (1U << rxq->elts_n) - 1); > + if (offset < used) > + return RTE_ETH_RX_DESC_DONE; > + return RTE_ETH_RX_DESC_AVAIL; > +} > + > +/** > * DPDK callback for TX. > * > * @param dpdk_txq > diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h > index 41a34d7..e864dcd 100644 > --- a/drivers/net/mlx5/mlx5_rxtx.h > +++ b/drivers/net/mlx5/mlx5_rxtx.h > @@ -323,6 +323,8 @@ uint16_t mlx5_tx_burst_mpw_inline(void *, struct rte_mbuf **, uint16_t); > uint16_t mlx5_rx_burst(void *, struct rte_mbuf **, uint16_t); > uint16_t removed_tx_burst(void *, struct rte_mbuf **, uint16_t); > uint16_t removed_rx_burst(void *, struct rte_mbuf **, uint16_t); > +int mlx5_rx_descriptor_status(struct rte_eth_dev *, uint16_t, uint16_t); > +int mlx5_tx_descriptor_status(struct rte_eth_dev *, uint16_t, uint16_t); > > /* mlx5_mr.c */ > > -- > 2.8.1 Acked-by: Nelio Laranjeiro -- Nélio Laranjeiro 6WIND