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From: Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
To: jerin.jacob@caviumnetworks.com, jianbo.liu@linaro.org,
	cristian.dumitrescu@intel.com
Cc: dev@dpdk.org, Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
Subject: [dpdk-dev] [PATCH 1/2] table: separate out arch specific defines from lru header
Date: Thu, 27 Apr 2017 06:47:27 -0700	[thread overview]
Message-ID: <20170427134728.35392-1-ashwin.sekhar@caviumnetworks.com> (raw)

* Moved all x86 related lru defines to rte_lru_x86.h while
  retaining all common defines in rte_lru.h
* Verified the changes with table_autotest unit test case

Signed-off-by: Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
---
 lib/librte_table/Makefile      |   1 +
 lib/librte_table/rte_lru.h     | 106 ++----------------------------
 lib/librte_table/rte_lru_x86.h | 145 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 152 insertions(+), 100 deletions(-)
 create mode 100644 lib/librte_table/rte_lru_x86.h

diff --git a/lib/librte_table/Makefile b/lib/librte_table/Makefile
index 0d06d36..f40cce7 100644
--- a/lib/librte_table/Makefile
+++ b/lib/librte_table/Makefile
@@ -69,6 +69,7 @@ SYMLINK-$(CONFIG_RTE_LIBRTE_TABLE)-include += rte_table_acl.h
 endif
 SYMLINK-$(CONFIG_RTE_LIBRTE_TABLE)-include += rte_table_hash.h
 SYMLINK-$(CONFIG_RTE_LIBRTE_TABLE)-include += rte_lru.h
+SYMLINK-$(CONFIG_RTE_LIBRTE_TABLE)-include += rte_lru_x86.h
 SYMLINK-$(CONFIG_RTE_LIBRTE_TABLE)-include += rte_table_array.h
 SYMLINK-$(CONFIG_RTE_LIBRTE_TABLE)-include += rte_table_stub.h
 
diff --git a/lib/librte_table/rte_lru.h b/lib/librte_table/rte_lru.h
index e87e062..2fe87c8 100644
--- a/lib/librte_table/rte_lru.h
+++ b/lib/librte_table/rte_lru.h
@@ -38,31 +38,13 @@
 extern "C" {
 #endif
 
-#include <stdint.h>
-
-#ifdef __INTEL_COMPILER
-#define GCC_VERSION (0)
+#ifdef RTE_ARCH_X86_64
+#include "rte_lru_x86.h"
 #else
-#define GCC_VERSION (__GNUC__ * 10000+__GNUC_MINOR__*100 + __GNUC_PATCHLEVEL__)
-#endif
-
-#ifndef RTE_TABLE_HASH_LRU_STRATEGY
-#ifdef __SSE4_2__
-#define RTE_TABLE_HASH_LRU_STRATEGY                        2
-#else /* if no SSE, use simple scalar version */
-#define RTE_TABLE_HASH_LRU_STRATEGY                        1
-#endif
-#endif
-
-#ifndef RTE_ARCH_X86_64
 #undef RTE_TABLE_HASH_LRU_STRATEGY
 #define RTE_TABLE_HASH_LRU_STRATEGY                        1
 #endif
 
-#if (RTE_TABLE_HASH_LRU_STRATEGY < 0) || (RTE_TABLE_HASH_LRU_STRATEGY > 3)
-#error Invalid value for RTE_TABLE_HASH_LRU_STRATEGY
-#endif
-
 #if RTE_TABLE_HASH_LRU_STRATEGY == 0
 
 #define lru_init(bucket)						\
@@ -118,87 +100,11 @@ do {									\
 		bucket->lru_list = x;					\
 } while (0)
 
-#elif RTE_TABLE_HASH_LRU_STRATEGY == 2
-
-#if GCC_VERSION > 40306
-#include <x86intrin.h>
-#else
-#include <emmintrin.h>
-#include <smmintrin.h>
-#include <xmmintrin.h>
-#endif
-
-#define lru_init(bucket)						\
-do									\
-	bucket->lru_list = 0x0000000100020003LLU;			\
-while (0)
-
-#define lru_pos(bucket) (bucket->lru_list & 0xFFFFLLU)
-
-#define lru_update(bucket, mru_val)					\
-do {									\
-	/* set up the masks for all possible shuffles, depends on pos */\
-	static uint64_t masks[10] = {					\
-		/* Shuffle order; Make Zero (see _mm_shuffle_epi8 manual) */\
-		0x0100070605040302, 0x8080808080808080,			\
-		0x0302070605040100, 0x8080808080808080,			\
-		0x0504070603020100, 0x8080808080808080,			\
-		0x0706050403020100, 0x8080808080808080,			\
-		0x0706050403020100, 0x8080808080808080};		\
-	/* load up one register with repeats of mru-val  */		\
-	uint64_t mru2 = mru_val;					\
-	uint64_t mru3 = mru2 | (mru2 << 16);				\
-	uint64_t lru = bucket->lru_list;				\
-	/* XOR to cause the word we're looking for to go to zero */	\
-	uint64_t mru = lru ^ ((mru3 << 32) | mru3);			\
-	__m128i c = _mm_cvtsi64_si128(mru);				\
-	__m128i b = _mm_cvtsi64_si128(lru);				\
-	/* Find the minimum value (first zero word, if it's in there) */\
-	__m128i d = _mm_minpos_epu16(c);				\
-	/* Second word is the index to found word (first word is the value) */\
-	unsigned pos = _mm_extract_epi16(d, 1);				\
-	/* move the recently used location to top of list */		\
-	__m128i k = _mm_shuffle_epi8(b, *((__m128i *) &masks[2 * pos]));\
-	/* Finally, update the original list with the reordered data */	\
-	bucket->lru_list = _mm_extract_epi64(k, 0);			\
-	/* Phwew! */							\
-} while (0)
-
-#elif RTE_TABLE_HASH_LRU_STRATEGY == 3
+#elif (RTE_TABLE_HASH_LRU_STRATEGY == 2) || (RTE_TABLE_HASH_LRU_STRATEGY == 3)
 
-#if GCC_VERSION > 40306
-#include <x86intrin.h>
-#else
-#include <emmintrin.h>
-#include <smmintrin.h>
-#include <xmmintrin.h>
-#endif
-
-#define lru_init(bucket)						\
-do									\
-	bucket->lru_list = ~0LLU;					\
-while (0)
-
-
-static inline int
-f_lru_pos(uint64_t lru_list)
-{
-	__m128i lst = _mm_set_epi64x((uint64_t)-1, lru_list);
-	__m128i min = _mm_minpos_epu16(lst);
-	return _mm_extract_epi16(min, 1);
-}
-#define lru_pos(bucket) f_lru_pos(bucket->lru_list)
-
-#define lru_update(bucket, mru_val)					\
-do {									\
-	const uint64_t orvals[] = {0xFFFFLLU, 0xFFFFLLU << 16,		\
-		0xFFFFLLU << 32, 0xFFFFLLU << 48, 0LLU};		\
-	const uint64_t decs[] = {0x1000100010001LLU, 0};		\
-	__m128i lru = _mm_cvtsi64_si128(bucket->lru_list);		\
-	__m128i vdec = _mm_cvtsi64_si128(decs[mru_val>>2]);		\
-	lru = _mm_subs_epu16(lru, vdec);				\
-	bucket->lru_list = _mm_extract_epi64(lru, 0) | orvals[mru_val];	\
-} while (0)
+/**
+ * These strategies are implemented in architecture specific header files.
+ */
 
 #else
 
diff --git a/lib/librte_table/rte_lru_x86.h b/lib/librte_table/rte_lru_x86.h
new file mode 100644
index 0000000..b55431b
--- /dev/null
+++ b/lib/librte_table/rte_lru_x86.h
@@ -0,0 +1,145 @@
+/*-
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of Intel Corporation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __INCLUDE_RTE_LRU_X86_H__
+#define __INCLUDE_RTE_LRU_X86_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#ifdef __INTEL_COMPILER
+#define GCC_VERSION (0)
+#else
+#define GCC_VERSION (__GNUC__ * 10000+__GNUC_MINOR__*100 + __GNUC_PATCHLEVEL__)
+#endif
+
+#ifndef RTE_TABLE_HASH_LRU_STRATEGY
+#ifdef __SSE4_2__
+#define RTE_TABLE_HASH_LRU_STRATEGY                        2
+#else /* if no SSE, use simple scalar version */
+#define RTE_TABLE_HASH_LRU_STRATEGY                        1
+#endif
+#endif
+
+#if RTE_TABLE_HASH_LRU_STRATEGY == 2
+
+#if GCC_VERSION > 40306
+#include <x86intrin.h>
+#else
+#include <emmintrin.h>
+#include <smmintrin.h>
+#include <xmmintrin.h>
+#endif
+
+#define lru_init(bucket)						\
+do									\
+	bucket->lru_list = 0x0000000100020003LLU;			\
+while (0)
+
+#define lru_pos(bucket) (bucket->lru_list & 0xFFFFLLU)
+
+#define lru_update(bucket, mru_val)					\
+do {									\
+	/* set up the masks for all possible shuffles, depends on pos */\
+	static uint64_t masks[10] = {					\
+		/* Shuffle order; Make Zero (see _mm_shuffle_epi8 manual) */\
+		0x0100070605040302, 0x8080808080808080,			\
+		0x0302070605040100, 0x8080808080808080,			\
+		0x0504070603020100, 0x8080808080808080,			\
+		0x0706050403020100, 0x8080808080808080,			\
+		0x0706050403020100, 0x8080808080808080};		\
+	/* load up one register with repeats of mru-val  */		\
+	uint64_t mru2 = mru_val;					\
+	uint64_t mru3 = mru2 | (mru2 << 16);				\
+	uint64_t lru = bucket->lru_list;				\
+	/* XOR to cause the word we're looking for to go to zero */	\
+	uint64_t mru = lru ^ ((mru3 << 32) | mru3);			\
+	__m128i c = _mm_cvtsi64_si128(mru);				\
+	__m128i b = _mm_cvtsi64_si128(lru);				\
+	/* Find the minimum value (first zero word, if it's in there) */\
+	__m128i d = _mm_minpos_epu16(c);				\
+	/* Second word is the index to found word (first word is the value) */\
+	unsigned pos = _mm_extract_epi16(d, 1);				\
+	/* move the recently used location to top of list */		\
+	__m128i k = _mm_shuffle_epi8(b, *((__m128i *) &masks[2 * pos]));\
+	/* Finally, update the original list with the reordered data */	\
+	bucket->lru_list = _mm_extract_epi64(k, 0);			\
+	/* Phwew! */							\
+} while (0)
+
+#elif RTE_TABLE_HASH_LRU_STRATEGY == 3
+
+#if GCC_VERSION > 40306
+#include <x86intrin.h>
+#else
+#include <emmintrin.h>
+#include <smmintrin.h>
+#include <xmmintrin.h>
+#endif
+
+#define lru_init(bucket)						\
+do									\
+	bucket->lru_list = ~0LLU;					\
+while (0)
+
+
+static inline int
+f_lru_pos(uint64_t lru_list)
+{
+	__m128i lst = _mm_set_epi64x((uint64_t)-1, lru_list);
+	__m128i min = _mm_minpos_epu16(lst);
+	return _mm_extract_epi16(min, 1);
+}
+#define lru_pos(bucket) f_lru_pos(bucket->lru_list)
+
+#define lru_update(bucket, mru_val)					\
+do {									\
+	const uint64_t orvals[] = {0xFFFFLLU, 0xFFFFLLU << 16,		\
+		0xFFFFLLU << 32, 0xFFFFLLU << 48, 0LLU};		\
+	const uint64_t decs[] = {0x1000100010001LLU, 0};		\
+	__m128i lru = _mm_cvtsi64_si128(bucket->lru_list);		\
+	__m128i vdec = _mm_cvtsi64_si128(decs[mru_val>>2]);		\
+	lru = _mm_subs_epu16(lru, vdec);				\
+	bucket->lru_list = _mm_extract_epi64(lru, 0) | orvals[mru_val];	\
+} while (0)
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
-- 
2.7.4

             reply	other threads:[~2017-04-27 13:47 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-27 13:47 Ashwin Sekhar T K [this message]
2017-04-27 13:47 ` [dpdk-dev] [PATCH 2/2] table: add neon version for lru strategy 3 Ashwin Sekhar T K
2017-04-28  8:58 ` [dpdk-dev] [PATCH v2 1/2] table: separate out arch specific defines from lru header Ashwin Sekhar T K
2017-04-28  8:58   ` [dpdk-dev] [PATCH v2 2/2] table: add neon version for lru strategy 3 Ashwin Sekhar T K
2017-07-03 15:17     ` Thomas Monjalon

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