From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id C6C0C37B4 for ; Tue, 20 Jun 2017 18:38:32 +0200 (CEST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP; 20 Jun 2017 09:38:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,364,1493708400"; d="scan'208";a="1143134268" Received: from unknown (HELO silpixa00399126.ger.corp.intel.com) ([10.237.223.223]) by orsmga001.jf.intel.com with ESMTP; 20 Jun 2017 09:38:19 -0700 From: Bruce Richardson To: Wenzhuo Lu , Konstantin Ananyev Cc: Bruce Richardson , dev@dpdk.org Date: Tue, 20 Jun 2017 16:23:10 +0100 Message-Id: <20170620152313.107642-16-bruce.richardson@intel.com> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170620152313.107642-1-bruce.richardson@intel.com> References: <20170620152313.107642-1-bruce.richardson@intel.com> Subject: [dpdk-dev] [PATCH 15/18] net/ixgbe: remove fallback code for non-SSE4 systems X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 20 Jun 2017 16:38:33 -0000 Since SSE4 is now part of minimum requirements for DPDK on x86, we no longer need this fallback code. Signed-off-by: Bruce Richardson --- drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c b/drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c index 203f092..d209bb2 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c +++ b/drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c @@ -216,26 +216,11 @@ desc_to_olflags_v(__m128i descs[4], __m128i mbuf_init, uint8_t vlan_flags, * appropriate flags means that we have to do a shift and blend for * each mbuf before we do the write. */ -#ifdef RTE_MACHINE_CPUFLAG_SSE4_2 - rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtag1, 8), 0x10); rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtag1, 6), 0x10); rearm2 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtag1, 4), 0x10); rearm3 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtag1, 2), 0x10); -#else - rearm0 = _mm_slli_si128(vtag1, 14); - rearm1 = _mm_slli_si128(vtag1, 12); - rearm2 = _mm_slli_si128(vtag1, 10); - rearm3 = _mm_slli_si128(vtag1, 8); - - rearm0 = _mm_or_si128(mbuf_init, _mm_srli_epi64(rearm0, 48)); - rearm1 = _mm_or_si128(mbuf_init, _mm_srli_epi64(rearm1, 48)); - rearm2 = _mm_or_si128(mbuf_init, _mm_srli_epi64(rearm2, 48)); - rearm3 = _mm_or_si128(mbuf_init, _mm_srli_epi64(rearm3, 48)); - -#endif /* RTE_MACHINE_CPUFLAG_SSE4_2 */ - /* write the rearm data and the olflags in one write */ RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) != offsetof(struct rte_mbuf, rearm_data) + 8); -- 2.9.4