From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg0-f52.google.com (mail-pg0-f52.google.com [74.125.83.52]) by dpdk.org (Postfix) with ESMTP id 15289968 for ; Thu, 31 Aug 2017 17:32:11 +0200 (CEST) Received: by mail-pg0-f52.google.com with SMTP id r133so2933581pgr.3 for ; Thu, 31 Aug 2017 08:32:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=networkplumber-org.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1kFTMXfPAgUW7pjLxCBcjGgQhvud9KPwi0xImr8nq2s=; b=De/eYDfEnbjfQEe21ig9j4bER0E3/miDco2IpdlMWPoYotvCKaFeC+Kh9VM2KWu3yX diZJdHk7zE5b6lrBBmPjuQYPSMSa1Vmg+QVraupsVE0OWIMSo7ZKRaxvZswdJESljdYg AhGX2SzYL3qf64Z8qM+4a4Suzzw8Sy7T8d5nyswdJ37U98OMmT3KANqom9PzyFsMxlsF tajB8mOJaz+t1/oscAW1FJA89FhYlKZa7PYEmfO59ddSaPyWlKMndd0dj8FgkPBAQeWy EFj5MqP++73TnH3/i8O3JdkbMQgAP2O3IMHMpbjrz1VhJPVI/asalWKk4rTRGJLiCHy/ x1Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1kFTMXfPAgUW7pjLxCBcjGgQhvud9KPwi0xImr8nq2s=; b=QY8wDcA6n0DUbFl79lrWcG1YHyEQNJOfjM3d3QhRFUKHbq3sB/i/m1sLDyLkN5ez/4 Hg91Zp+j5DtQKgW32XewKRFxJ3qDnZxEMeX+6Hfu65w5RGO860fk08U7BnBKuhqncy8c 5wogT5/yYPF0OZlAHu409ed4HQT2psFvPnF98yExjT65gf6e0abLPyYInrH5pfi5kgXV RJZR2x3q0ZBimO+ZQhpxhNMJqwy/kM0I/0FvWFZqpDVaVlJwsg+pPwKS/oZzU9AU+Wc5 5D0ssE+9tSZpWIj4fnStZwr1Wo7gWHcmXTO75IK/cFgOd6Whz2waAUyP5Tap6baZdS9m qaJg== X-Gm-Message-State: AHYfb5g0J7s8kRPPAW32oUJOc8/zwTn42708s1GvlWxIox2tR5QYYIxI PwshWUaibKPdsHZopG2a0A== X-Google-Smtp-Source: ADKCNb4Vo+9goKJfwL9z53/LV+Mf2dZxLuYJwdNUMXHnHX0v3g1DEb8MmPD6ZIOmS2FzshKQAa5Ctg== X-Received: by 10.84.217.222 with SMTP id d30mr3163066plj.364.1504193530282; Thu, 31 Aug 2017 08:32:10 -0700 (PDT) Received: from xeon-e3 (76-14-207-240.or.wavecable.com. [76.14.207.240]) by smtp.gmail.com with ESMTPSA id r86sm13679151pfi.161.2017.08.31.08.32.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 31 Aug 2017 08:32:10 -0700 (PDT) Date: Thu, 31 Aug 2017 08:32:07 -0700 From: Stephen Hemminger To: Markus Theil Cc: dev@dpdk.org, ferruh.yigit@intel.com Message-ID: <20170831083207.3a95c3a7@xeon-e3> In-Reply-To: <1504174949-25656-3-git-send-email-markus.theil@tu-ilmenau.de> References: <1503408514-20079-1-git-send-email-markus.theil@tu-ilmenau.de> <1504174949-25656-1-git-send-email-markus.theil@tu-ilmenau.de> <1504174949-25656-3-git-send-email-markus.theil@tu-ilmenau.de> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: [dpdk-dev] [PATCH v4 3/3] igb_uio: MSI IRQ mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 Aug 2017 15:32:11 -0000 On Thu, 31 Aug 2017 12:22:29 +0200 Markus Theil wrote: > +/* > + * It masks the msi on/off of generating MSI messages. > + */ > +static void > +igbuio_msi_mask_irq(struct pci_dev *pdev, struct msi_desc *desc, int32_t state) > +{ > + u32 mask_bits = desc->masked; > + u32 offset = desc->irq - pdev->irq; > + u32 mask = 1 << offset; > + u32 flag = !!state << offset; > + > + if (!desc->msi_attrib.maskbit) > + return; > + > + mask_bits &= ~mask; > + mask_bits |= flag; > + > + if (mask_bits != desc->masked) { > + pci_write_config_dword(pdev, desc->mask_pos, mask_bits); > + desc->masked = mask_bits; > + } > +} > + Why not use the existing kernel API pci_msi_mask_irq()?