From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg0-f44.google.com (mail-pg0-f44.google.com [74.125.83.44]) by dpdk.org (Postfix) with ESMTP id 96397293B for ; Tue, 5 Sep 2017 19:29:10 +0200 (CEST) Received: by mail-pg0-f44.google.com with SMTP id d8so10576451pgt.4 for ; Tue, 05 Sep 2017 10:29:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=networkplumber-org.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=I1VEV2trpei4KaOoyC8m9KbjB8Jruc2t11yseBG/AhA=; b=L8a+N2f+Q0euy+uxSZ+VtXoj5OG/xLmn2u4ndgQ1vXlzpFaJ0HWJWU3TujOsKRVjRK 8LYdOM8gsR7wttiO9oa6JmWzDEh6eYmqq6M23W12osA+G+f+38XMbTAyimngEoazoJr7 41Q6449rygmzXSpu9FF6rzX58QNV2VdSO5JGcY8IHVi91TmfeJyBXhNvAtYZunTa0ScI di7vzi1leN/Pnhdmz/cPbZP8rcgMG3SkE0the0l5rg85GUnq7adxeY2J2XU4Q8HpK0wt lWBH7CsLXppVjI/WzFDezuf5onf/li4s6l4ztUrMHqE0OALMhWc5HYiMF4rfIdvvXE6K Hr8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=I1VEV2trpei4KaOoyC8m9KbjB8Jruc2t11yseBG/AhA=; b=Ueq4+OT2Hv1/b6krSFQoeIS5U9FDR/GKbXI3GmlZy56JsYF6XJg3soLVo6Z/084l1j yvOLmCikiYpWEshwK/pPFX3ZaKsqhJHD2R20Ruf98zNbT8dNsSVsDImy0CbBuZ3yfoHq TbmCF4c6ShEHF+eA+fJdHao6qQbRWAouISmdcPaQlvIZFMzzLDv1/+35v23cjH6j5IwX 5mU9QwA25tCYMbxIJcCGlaLNzcVyYFREwisRHlfKv4YxqdfwTrO4HJK4JhjnjFvEjfTA csh6savCV4dvmRHWyHUUuhSxa+5ryn48i2v9P704UVWdmYB5GL2mLUrMoNfKcK95ntrr +Swg== X-Gm-Message-State: AHPjjUgnKXbsZSzt10GzTMR+vLcXvsBFJtnFhQtNxV4cGnVq6QzMytjN o8fsIBryBoKNlbVT X-Google-Smtp-Source: ADKCNb5aOtOBQNzNvYvH5tRkG9uFl2LrMUcMIVByXMn7NubV166uONk0hq5zZg8XRg17P8umbDYGyw== X-Received: by 10.84.210.108 with SMTP id z99mr5091791plh.341.1504632549031; Tue, 05 Sep 2017 10:29:09 -0700 (PDT) Received: from xeon-e3 (76-14-207-240.or.wavecable.com. [76.14.207.240]) by smtp.gmail.com with ESMTPSA id i187sm1895016pfe.71.2017.09.05.10.29.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Sep 2017 10:29:08 -0700 (PDT) Date: Tue, 5 Sep 2017 10:29:01 -0700 From: Stephen Hemminger To: Pavan Nikhilesh Cc: dev@dpdk.org, cristian.dumitrescu@intel.com Message-ID: <20170905102901.0d9db417@xeon-e3> In-Reply-To: <1504608532-18598-2-git-send-email-pbhagavatula@caviumnetworks.com> References: <1504608532-18598-1-git-send-email-pbhagavatula@caviumnetworks.com> <1504608532-18598-2-git-send-email-pbhagavatula@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: [dpdk-dev] [PATCH v4 2/3] eal: add u64 bit variant for reciprocal X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Sep 2017 17:29:10 -0000 On Tue, 5 Sep 2017 16:18:51 +0530 Pavan Nikhilesh wrote: > +/** > + * Unsigned 32-bit divisor structure. > + */ > +struct rte_reciprocal_u32 { > uint32_t m; > uint8_t sh1, sh2; > -}; > +} __rte_cache_aligned; > + > +/** > + * Unsigned 64-bit divisor structure. > + */ > +struct rte_reciprocal_u64 { > + uint64_t m; > + uint8_t sh1; > +} __rte_cache_aligned; I understand you want to squeeze every cycle out but it is not required that each of these structures always be cache aligned. They maybe embedded in other structures and having the structure padded so that these elements are cache aligned would take up more space and make cache performance worse. Better off to not put attributes on the structure definitions, and instead let usages of this feature align where appropriate.