From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 422ED1B1A0 for ; Wed, 20 Sep 2017 12:58:19 +0200 (CEST) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Sep 2017 03:58:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,421,1500966000"; d="scan'208";a="130625713" Received: from silpixa00399126.ir.intel.com (HELO silpixa00399126.ger.corp.intel.com) ([10.237.223.223]) by orsmga004.jf.intel.com with ESMTP; 20 Sep 2017 03:58:17 -0700 From: Bruce Richardson To: dev@dpdk.org Cc: Bruce Richardson Date: Wed, 20 Sep 2017 11:51:07 +0100 Message-Id: <20170920105107.153935-4-bruce.richardson@intel.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170920105107.153935-1-bruce.richardson@intel.com> References: <20170920105107.153935-1-bruce.richardson@intel.com> Subject: [dpdk-dev] [PATCH 3/3] build/x86: add SSE cpuflags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Sep 2017 10:58:19 -0000 Previous code only added in AVX, and a few other non-SSE flags to the compile-time cpuflags because all SSE instruction set levels are now required for an x86 build. However, some apps may still be checking for the existing SSE ones in the legacy build system, so add them here for completeness and compatibility. Signed-off-by: Bruce Richardson --- config/x86/meson.build | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/config/x86/meson.build b/config/x86/meson.build index 0d1a532ad..c05c2f418 100644 --- a/config/x86/meson.build +++ b/config/x86/meson.build @@ -40,6 +40,12 @@ if cc.get_define('__SSE4_2__', args: march_opt) == '' error(sse_errormsg) endif +base_flags = ['SSE', 'SSE2', 'SSE3','SSSE3', 'SSE4_1', 'SSE4_2'] +foreach f:base_flags + dpdk_conf.set('RTE_MACHINE_CPUFLAG_' + f, 1) + compile_time_cpuflags += ['RTE_CPUFLAG_' + f] +endforeach + dpdk_conf.set('RTE_ARCH_X86', 1) if (host_machine.cpu_family() == 'x86_64') dpdk_conf.set('RTE_ARCH_X86_64', 1) @@ -66,5 +72,9 @@ if cc.get_define('__AVX2__', args: march_opt) != '' dpdk_conf.set('RTE_MACHINE_CPUFLAG_AVX2', 1) compile_time_cpuflags += ['RTE_CPUFLAG_AVX2'] endif +if cc.get_define('__AVX512F__', args: march_opt) != '' + dpdk_conf.set('RTE_MACHINE_CPUFLAG_AVX512F', 1) + compile_time_cpuflags += ['RTE_CPUFLAG_AVX512F'] +endif dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64) -- 2.13.5