From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-f181.google.com (mail-wr0-f181.google.com [209.85.128.181]) by dpdk.org (Postfix) with ESMTP id 1D5521B19C for ; Thu, 21 Sep 2017 13:49:39 +0200 (CEST) Received: by mail-wr0-f181.google.com with SMTP id l22so4399465wrc.10 for ; Thu, 21 Sep 2017 04:49:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=KUzRLUkjWvaTtERrNsNK6akJMTsFm/5sy9pXt6Txml0=; b=HEfd/q8OsNokEu6fRdDjhr5y7BJmWTI3fit5Kuzn5Z0bUY8CSz5IGkZcJtYtxgUCLH 9P5JW1rE3TGvI0ZhqCKeglt3Yj4SNJ3Yr4vB2f0ogqGWA/gkvnctSAUPDlMxIJg4V+Ti +2OD2isp9SMsZ4YRKMWrdS2rvNKgqo9yawvGM8nRuzWtypjOJSk3OmmLL00nTjFcvXI0 i0yp2y4IjRXrr7GBNS34ALju7SM57mXa4MVOI0ZqN8olSw+bpiB/8SNF320lHcfiAM55 76kyq/o3iBbHW52V0hIHoBtREitWbPwIWyYYfywhwYna0Ifr+jwbHuR7N4Y1r58mOS2H ImeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=KUzRLUkjWvaTtERrNsNK6akJMTsFm/5sy9pXt6Txml0=; b=YHPSpKD+LaTLsmjcg2c0LIbsIgZD5MUA2TBTk0Gz6EO4ZSemJ9Zin36Mi0eYZKIRi2 OMWxylmDuYNfoPyVFmX2DLIeO/H8i50PH7oYj8RMEC7dUoA/VeEeAwQ2ICoknsCfyy3H O23xpPLDPcA2H5YCuV8XJK2iGXOdJ+/+izOKLViwhYHtGt4efJOr66QQlV0mDZRi2AnE DI5C8DY5LQXdV2STax31rXduJsEg4HW9wA/TGPpNvIw8nVw6SSc6z3DsngraDoV8V2PS JhqI2aqX9UAHk+kyAfAM71tfoVGS3dD64L4s2ikoeh5D/BObvZOL8xu/vwc0CwVPxkWV 9TrA== X-Gm-Message-State: AHPjjUhPdNHu7iN3aVvYP9+to7A20q2PfLxLwyS0bKThLKCOztTiCeWx axrBQNsaV2wrD0b8KUU2DMckeQ== X-Google-Smtp-Source: AOwi7QCGeC8svG2iGn+VagyIK8LV3GZZCoB18Y0ySw4/91UEI3khV0lfKOwB8vBSDBs/te5AWGtI5Q== X-Received: by 10.223.148.165 with SMTP id 34mr1606191wrr.20.1505994579535; Thu, 21 Sep 2017 04:49:39 -0700 (PDT) Received: from 6wind.com (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id l15sm1229069wrl.47.2017.09.21.04.49.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Sep 2017 04:49:38 -0700 (PDT) Date: Thu, 21 Sep 2017 13:49:28 +0200 From: Adrien Mazarguil To: Zhiyong Yang Cc: dev@dpdk.org, thomas@monjalon.net, ferruh.yigit@intel.com Message-ID: <20170921114928.GC11375@6wind.com> References: <20170909144727.46388-1-zhiyong.yang@intel.com> <20170921083243.57991-1-zhiyong.yang@intel.com> <20170921083243.57991-3-zhiyong.yang@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170921083243.57991-3-zhiyong.yang@intel.com> Subject: Re: [dpdk-dev] [PATCH v4 2/5] ethdev: increase port_id range X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Sep 2017 11:49:40 -0000 On Thu, Sep 21, 2017 at 04:32:40PM +0800, Zhiyong Yang wrote: > Extend port_id definition from uint8_t to uint16_t in lib and drivers > data structures, specifically rte_eth_dev_data. Modify the APIs, > drivers and app using port_id at the same time. > > Fix some checkpatch issues from the original code and remove some > unnecessary cast operations. > > release_17_11 and deprecation have been updated in the patch. > > Signed-off-by: Zhiyong Yang > --- > diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h > index 7de1d1086..238a64f43 100644 > --- a/drivers/net/mlx5/mlx5_rxtx.h > +++ b/drivers/net/mlx5/mlx5_rxtx.h > @@ -112,14 +112,14 @@ struct rxq { > unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */ > unsigned int cqe_n:4; /* Log 2 of CQ elements. */ > unsigned int elts_n:4; /* Log 2 of Mbufs. */ > - unsigned int port_id:8; > unsigned int rss_hash:1; /* RSS hash result is enabled. */ > unsigned int mark:1; /* Marked flow available on the queue. */ > unsigned int pending_err:1; /* CQE error needs to be handled. */ > unsigned int trim_elts:1; /* Whether elts needs clean-up. */ > - unsigned int :6; /* Remaining bits. */ > + unsigned int :14; /* Remaining bits. */ > volatile uint32_t *rq_db; > volatile uint32_t *cq_db; > + uint16_t port_id; > uint16_t rq_ci; > uint16_t rq_pi; > uint16_t cq_ci; Can't speak for the other PMDs, but it looks OK as far as mlx4/mlx5 are affected. This is my ack for this specific change: Acked-by: Adrien Mazarguil -- Adrien Mazarguil 6WIND