From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM03-CO1-obe.outbound.protection.outlook.com (mail-co1nam03on0067.outbound.protection.outlook.com [104.47.40.67]) by dpdk.org (Postfix) with ESMTP id 638A91B600 for ; Fri, 13 Oct 2017 03:49:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=TRx9B+GtyqG3Ixh7GphT2Qm+sDkA+v4LDRjXvc6ziNU=; b=EN2jZ9nYLok65YiuZz7SKYWzcOTCXAID6yy08HVisLETiA0dQXdFzQWlyvq/dQkUB5yasMm60dJwLx2EYTPR4w2jPzbfASrfzKr6PU+m6ErJWAcwiImmYftNjO5GZWH9n+6YR4xT65I7nwWmQhQNhUuC66k4DjJUgDIAWUwiy/g= Received: from jerin (106.201.58.193) by SN2PR07MB2525.namprd07.prod.outlook.com (10.167.14.153) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.77.7; Fri, 13 Oct 2017 01:49:37 +0000 Date: Fri, 13 Oct 2017 07:19:16 +0530 From: Jerin Jacob To: Jia He Cc: "Ananyev, Konstantin" , Olivier MATZ , "dev@dpdk.org" , "jia.he@hxt-semitech.com" , "jie2.liu@hxt-semitech.com" , "bing.zhao@hxt-semitech.com" Message-ID: <20171013014914.GA2067@jerin> References: <20171010095636.4507-1-hejianet@gmail.com> <20171012155350.j34ddtivxzd27pag@platinum> <2601191342CEEE43887BDE71AB9772585FAA859F@IRSMSX103.ger.corp.intel.com> <20171012172311.GA8524@jerin> MIME-Version: 1.0 Content-Type: text/plain; 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WOW64; rv:52.0) Gecko/20100101 > Thunderbird/52.3.0 > > Hi > > > On 10/13/2017 9:02 AM, Jia He Wrote: > > Hi Jerin > > > > > > On 10/13/2017 1:23 AM, Jerin Jacob Wrote: > > > -----Original Message----- > > > > Date: Thu, 12 Oct 2017 17:05:50 +0000 > > > > > [...] > > > On the same lines, > > > > > > Jia He, jie2.liu, bing.zhao, > > > > > > Is this patch based on code review or do you saw this issue on any > > > of the > > > arm/ppc target? arm64 will have performance impact with this change. > sorry, miss one important information > Our platform is an aarch64 server with 46 cpus. Is this an OOO(Out of order execution) aarch64 CPU implementation? > If we reduced the involved cpu numbers, the bug occurred less frequently. > > Yes, mb barrier impact the performance, but correctness is more important, > isn't it ;-) Yes. > Maybe we can  find any other lightweight barrier here? Yes, Regarding the lightweight barrier, arm64 has native support for acquire and release semantics, which is exposed through gcc as architecture agnostic functions. https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html http://preshing.com/20130922/acquire-and-release-fences/ Good to know, 1) How much overhead this patch in your platform? Just relative numbers are enough 2) As a prototype, Is Changing to acquire and release schematics reduces the overhead in your platform? Reference FreeBSD ring/DPDK style ring implementation through acquire and release schematics https://github.com/Linaro/odp/blob/master/platform/linux-generic/pktio/ring.c I will also spend on cycles on this. > > Cheers, > Jia > > Based on mbuf_autotest, the rte_panic will be invoked in seconds. > > > > PANIC in test_refcnt_iter(): > > (lcore=0, iter=0): after 10s only 61 of 64 mbufs left free > > 1: [./test(rte_dump_stack+0x38) [0x58d868]] > > Aborted (core dumped) > > > > Cheers, > > Jia > > > > > > > > > > Konstantin > > >