From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM03-CO1-obe.outbound.protection.outlook.com (mail-co1nam03on0062.outbound.protection.outlook.com [104.47.40.62]) by dpdk.org (Postfix) with ESMTP id B18091B864 for ; Wed, 25 Oct 2017 15:27:13 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=hGYiCV5a9eSSvh0fBJWSINJDS01X3qa0S7FgWKxwDVU=; b=mXH1QC7uQXcde2YbAKr/sat2X1lNCHcvcb9wzaf52uYlOOHlNBxzOjEIAO0vDgKXUimT7dawHO+VXmU6FqoulAHAN14JfGZF74UJGwZNvI4IHgOjEK4e3h5QPyk/NSyS7Z6n3nudvqn7Z8h8nK6H69QmGEsDKV+birJt/9uBPiI= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Jerin.JacobKollanukkaran@cavium.com; Received: from jerin (111.93.218.67) by SN2PR07MB2526.namprd07.prod.outlook.com (2603:10b6:804:6::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.156.4; Wed, 25 Oct 2017 13:27:07 +0000 Date: Wed, 25 Oct 2017 18:56:54 +0530 From: Jerin Jacob To: Jia He Cc: "Ananyev, Konstantin" , "Zhao, Bing" , Olivier MATZ , "dev@dpdk.org" , "jia.he@hxt-semitech.com" , "jie2.liu@hxt-semitech.com" , "bing.zhao@hxt-semitech.com" , "Richardson, Bruce" Message-ID: <20171025132642.GA13977@jerin> References: <2601191342CEEE43887BDE71AB9772585FAAB171@IRSMSX103.ger.corp.intel.com> <8806e2bd-c57b-03ff-a315-0a311690f1d9@163.com> <2601191342CEEE43887BDE71AB9772585FAAB404@IRSMSX103.ger.corp.intel.com> <2601191342CEEE43887BDE71AB9772585FAAB570@IRSMSX103.ger.corp.intel.com> <3e580cd7-2854-d855-be9c-7c4ce06e3ed5@gmail.com> <20171020054319.GA4249@jerin> <20171023100617.GA17957@jerin> MIME-Version: 1.0 Content-Type: text/plain; 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WOW64; rv:52.0) Gecko/20100101 > Thunderbird/52.4.0 > > Hi Jerin Hi Jia, > > example: > > ./build/app/test -c 0xff -n 4 > > > > ring_perf_autotest > Seem in our arm64 server, the ring_perf_autotest will be finished in a few > seconds: Yes. It just need a few seconds. > Anything wrong about configuration or environment setup? By default, arm64+dpdk will be using el0 counter to measure the cycles. I think, in your SoC, it will be running at 50MHz or 100MHz.So, You can follow the below scheme to get accurate cycle measurement scheme: See: http://dpdk.org/doc/guides/prog_guide/profile_app.html check: 44.2.2. High-resolution cycle counter > > root@ubuntu:/home/hj/dpdk/build/build/test/test# ./test -c 0xff -n 4 > EAL: Detected 44 lcore(s) > EAL: Probing VFIO support... > APP: HPET is not enabled, using TSC as default timer > RTE>>per_lcore_autotest > RTE>>ring_perf_autotest > ### Testing single element and burst enq/deq ### > SP/SC single enq/dequeue: 0 > MP/MC single enq/dequeue: 2 > SP/SC burst enq/dequeue (size: 8): 0 If you follow the above link, The value '0' will be replaced with more meaning full data. > MP/MC burst enq/dequeue (size: 8): 0 > SP/SC burst enq/dequeue (size: 32): 0 > MP/MC burst enq/dequeue (size: 32): 0 > > ### Testing empty dequeue ### > SC empty dequeue: 0.02 > MC empty dequeue: 0.04 > > ### Testing using a single lcore ### > SP/SC bulk enq/dequeue (size: 8): 0.12 > MP/MC bulk enq/dequeue (size: 8): 0.31 > SP/SC bulk enq/dequeue (size: 32): 0.05 > MP/MC bulk enq/dequeue (size: 32): 0.09 > > ### Testing using two hyperthreads ### > SP/SC bulk enq/dequeue (size: 8): 0.12 > MP/MC bulk enq/dequeue (size: 8): 0.39 > SP/SC bulk enq/dequeue (size: 32): 0.04 > MP/MC bulk enq/dequeue (size: 32): 0.12 > > ### Testing using two physical cores ### > SP/SC bulk enq/dequeue (size: 8): 0.37 > MP/MC bulk enq/dequeue (size: 8): 0.92 > SP/SC bulk enq/dequeue (size: 32): 0.12 > MP/MC bulk enq/dequeue (size: 32): 0.26 > Test OK > RTE>> > > Cheers, > Jia > > By default, arm64+dpdk will be using el0 counter to measure the cycles. I > > think, in your SoC, it will be running at 50MHz or 100MHz.So, You can > > follow the below scheme to get accurate cycle measurement scheme: > > > > See: http://dpdk.org/doc/guides/prog_guide/profile_app.html > > check: 44.2.2. High-resolution cycle counter >