From: Jerin Jacob <jerin.jacob@caviumnetworks.com>
To: dev@dpdk.org
Cc: thomas@monjalon.net, jia.he@hxt-semitech.com,
Jerin Jacob <jerin.jacob@caviumnetworks.com>
Subject: [dpdk-dev] [PATCH] config/thunderx: disable c11 mem model ring implementation
Date: Sun, 3 Dec 2017 18:07:30 +0530 [thread overview]
Message-ID: <20171203123730.26782-1-jerin.jacob@caviumnetworks.com> (raw)
On thunderx and octeontx, ring_perf_autotest and
ring_pmd_perf_autotest test shows better performance
when disabling CONFIG_RTE_RING_USE_C11_MEM_MODEL.
On the other hand, Enabling CONFIG_RTE_RING_USE_C11_MEM_MODEL
shows better performance on thunderx2.
Since thunderx2 is using the default armv8 config,
no particular change is required.
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
---
This patch is depended on following patch from Jia He.
support c11 memory model barrier in librte_ring
http://dpdk.org/ml/archives/dev/2017-November/082368.html
---
config/defconfig_arm64-thunderx-linuxapp-gcc | 1 +
1 file changed, 1 insertion(+)
diff --git a/config/defconfig_arm64-thunderx-linuxapp-gcc b/config/defconfig_arm64-thunderx-linuxapp-gcc
index 45038b119..60c68ec96 100644
--- a/config/defconfig_arm64-thunderx-linuxapp-gcc
+++ b/config/defconfig_arm64-thunderx-linuxapp-gcc
@@ -36,6 +36,7 @@ CONFIG_RTE_MACHINE="thunderx"
CONFIG_RTE_CACHE_LINE_SIZE=128
CONFIG_RTE_MAX_NUMA_NODES=2
CONFIG_RTE_MAX_LCORE=96
+CONFIG_RTE_RING_USE_C11_MEM_MODEL=n
#
# Compile PMD for octeontx sso event device
--
2.15.1
next reply other threads:[~2017-12-03 12:38 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-03 12:37 Jerin Jacob [this message]
2018-01-29 15:14 ` Thomas Monjalon
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