From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-f193.google.com (mail-wr0-f193.google.com [209.85.128.193]) by dpdk.org (Postfix) with ESMTP id 21CD7293B for ; Wed, 6 Dec 2017 17:23:00 +0100 (CET) Received: by mail-wr0-f193.google.com with SMTP id a41so4516565wra.6 for ; Wed, 06 Dec 2017 08:23:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=lK1zCT/bC6t70cZPCdYOpP5iM0/W4zMWoINzeZ8LNUI=; b=fM3aQEvNM5xuun5Hmr0s5FKaAs4BM1TlNnEFgIgsI1rJkAlDVzxUMjnG68m+YANnkg CYODiQFheX+pAstvZfgG63VMKQkA/VW1gT3ESZNkvSFgGyTQh6+kKEuogeeRSIbVv33P 7ducL9jpm+67ZXU6/WftbmpiViDMXnTFAiwxRIGwJoSZUMYraFg3vCmqtQ8O10dPbDGo qkEvmPfhcmhNbGbTVLG4BPw2qyv5BGMFNm4Kex6j8qUhHBK8UGQ0vNj117EYQTjLMUX0 s/vwebQvu7i070uqJ30Yyy1bPnzLKVGUdNTyQjaMhjQi7ar3HgpiBOi5NWahQx4+peLl EojA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=lK1zCT/bC6t70cZPCdYOpP5iM0/W4zMWoINzeZ8LNUI=; b=LLOaY2cJpEHgYC/+wsYEYQIouUcmyxY1JXMcDtOVmxHUFAw6MeXmfno1uDZ1gZm3cw BzpyudLc77p1VRonxT059Y+wudgonsaOQP658Rxe3/ldtv1k05Yemd1YfXYYu1eNwxhD H6ftaJjbKm1xdUarlYEeUsSVvwrWd2zj9ivDDUREzshgBpynoUVkyc6AO/DwiuSyF7ht rpfgBG6TrBM7F0NIIOlpVWpWW4pV1eb7ccuUfKVyR/WI1i5TX9ZdA6a+s/QYkXeTnOBH vVq4SICJpKtYflSqty8/cQlK+6fJ6G3eVVZG7JaBdr5C8E2uJJwwqmzGw4TXOoF2OddA 94mg== X-Gm-Message-State: AJaThX6Y9JahXsgT06W/lhJ/zNwtROlewgJHuu5ECd2UknED1+yvEE6N a/u9t5NGlB+AyoCJ38fukD4muw== X-Google-Smtp-Source: AGs4zMYYzifrHo2KTOB7dw66crPCBbq+iMHdUinRDkW9JoCHKcd4W9IQHG6LjCJZO0u9nq+yB36WnQ== X-Received: by 10.223.158.147 with SMTP id a19mr22221513wrf.179.1512577379859; Wed, 06 Dec 2017 08:22:59 -0800 (PST) Received: from 6wind.com (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id i8sm3351071wmh.42.2017.12.06.08.22.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Dec 2017 08:22:59 -0800 (PST) Date: Wed, 6 Dec 2017 17:22:47 +0100 From: Adrien Mazarguil To: Matan Azrad Cc: dev@dpdk.org Message-ID: <20171206162247.GI4062@6wind.com> References: <1511871570-16826-1-git-send-email-matan@mellanox.com> <1512571693-15338-1-git-send-email-matan@mellanox.com> <1512571693-15338-8-git-send-email-matan@mellanox.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1512571693-15338-8-git-send-email-matan@mellanox.com> Subject: Re: [dpdk-dev] [PATCH v2 7/8] net/mlx4: align Tx descriptors number X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Dec 2017 16:23:00 -0000 On Wed, Dec 06, 2017 at 02:48:12PM +0000, Matan Azrad wrote: > Using power of 2 descriptors number makes the ring management easier > and allows to use mask operation instead of wraparound conditions. > > Adjust Tx descriptor number to be power of 2 and change calculation to > use mask accordingly. > > Signed-off-by: Matan Azrad > --- > drivers/net/mlx4/mlx4_rxtx.c | 28 +++++++++++++--------------- > drivers/net/mlx4/mlx4_txq.c | 13 +++++++++---- > 2 files changed, 22 insertions(+), 19 deletions(-) > > diff --git a/drivers/net/mlx4/mlx4_rxtx.c b/drivers/net/mlx4/mlx4_rxtx.c > index 8b8d95e..14192fe 100644 > --- a/drivers/net/mlx4/mlx4_rxtx.c > +++ b/drivers/net/mlx4/mlx4_rxtx.c > @@ -312,10 +312,14 @@ struct pv { > * > * @param txq > * Pointer to Tx queue structure. > + * @param sq > + * Pointer to the SQ structure. > + * @param elts_m > + * Tx elements number mask. It's minor however these parameters should be described in the same order as they appear in the function prototype, please swap them if you send an updated series. > */ > static void > -mlx4_txq_complete(struct txq *txq, const unsigned int elts_n, > - struct mlx4_sq *sq) > +mlx4_txq_complete(struct txq *txq, const unsigned int elts_m, > + struct mlx4_sq *sq) > { > diff --git a/drivers/net/mlx4/mlx4_txq.c b/drivers/net/mlx4/mlx4_txq.c > index 4c7b62a..7eb4b04 100644 > --- a/drivers/net/mlx4/mlx4_txq.c > +++ b/drivers/net/mlx4/mlx4_txq.c > @@ -76,17 +76,16 @@ > unsigned int elts_head = txq->elts_head; > unsigned int elts_tail = txq->elts_tail; > struct txq_elt (*elts)[txq->elts_n] = txq->elts; > + unsigned int elts_m = txq->elts_n - 1; > > DEBUG("%p: freeing WRs", (void *)txq); > while (elts_tail != elts_head) { > - struct txq_elt *elt = &(*elts)[elts_tail]; > + struct txq_elt *elt = &(*elts)[elts_tail++ & elts_m]; > > assert(elt->buf != NULL); > rte_pktmbuf_free(elt->buf); > elt->buf = NULL; > elt->wqe = NULL; > - if (++elts_tail == RTE_DIM(*elts)) > - elts_tail = 0; > } > txq->elts_tail = txq->elts_head; > } > @@ -208,7 +207,7 @@ struct txq_mp2mr_mbuf_check_data { > struct mlx4dv_obj mlxdv; > struct mlx4dv_qp dv_qp; > struct mlx4dv_cq dv_cq; > - struct txq_elt (*elts)[desc]; > + struct txq_elt (*elts)[rte_align32pow2(desc)]; OK, I'm curious about what happened to the magic 0x1000 though? Was it a limitation or some leftover debugging code? -- Adrien Mazarguil 6WIND