From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-f65.google.com (mail-wm0-f65.google.com [74.125.82.65]) by dpdk.org (Postfix) with ESMTP id C1CF47D30 for ; Fri, 5 Jan 2018 17:53:29 +0100 (CET) Received: by mail-wm0-f65.google.com with SMTP id n138so3544817wmg.2 for ; Fri, 05 Jan 2018 08:53:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=gd9XmYlGZIvmThqaxP0T5SXKE1L2igpxc6vfDNYgaZc=; b=TRklWEfBdGXuJM2Ru2drpxn1Hac13Y7eSu9xCEkQQmQ7bBYsUNJ721zfOpcNE2QhLm NQeo8zF4XNuHVNtb0fcZJ42x8R78OvPlEdHM9PWqCXVb10VZJ4F0jxvJSKRgwDUE/BCT j4NObxaMsiDUC30ZxRacz3wICyOlXnSfo7lElIulP1nMVkMzP6KiB+5i7bmTAF95sJDC PG5xoqyelfV5qvGFInXZ9vglsmTMSTN6OraxmguBioNUW0AueV4qeSNYOFBj24M1kt1j 9d2UM9tpZdoF1dpnlp8YclkiiCplH9pYnPKTIpPxBBL0xwEWoxbXz1gqZYd33IsrAOJe blvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=gd9XmYlGZIvmThqaxP0T5SXKE1L2igpxc6vfDNYgaZc=; b=OeMVCm+2Og7SrdJwFCIWtIRF24bEfQdSFgW59FP0tVs7sZFD/1A7WUAIds9SpYmvPW ov73Lhzqn59HOWE/8Prxn82pZBPD3sNGtivUHncpIqlUEEkxV55ZhGMDR/mTzJGtqTHR jzCmzzUiIIi8jrOaYCQkkVzQYBrbhX+u7k78YbkWGkaFkCKIIaR0K/ZYAY66heFrkw/w lUSLzuUEuwtc39J41FENvzxI4P2YZ8xRWkJOyMQsx1PSA/oA/q8PV/GWV2Wom8yxAfaM V7VmnFmg0ZrCkqrPDiW9MSGFVRMvbpAMfTasrsJsb7/3C5wwo676CQGoTToN140dlyrh lWpA== X-Gm-Message-State: AKGB3mKjayHJzy7nnZNrV151H96WCsDQZCwJ/4GQ8HVX7r/CH0fthDN2 zaNLP4j5bTTYFOfxXSCIYG3U4g== X-Google-Smtp-Source: ACJfBovuY+lBwtmnyH9oLJ2dyukunc3zc5P3j6U04oWeHTwMyrlTL5fixQTxp1BiGv8rnuJlhql1HQ== X-Received: by 10.80.137.164 with SMTP id g33mr4910742edg.29.1515171209440; Fri, 05 Jan 2018 08:53:29 -0800 (PST) Received: from 6wind.com (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id k19sm4197527ede.35.2018.01.05.08.53.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Jan 2018 08:53:28 -0800 (PST) Date: Fri, 5 Jan 2018 17:53:17 +0100 From: Adrien Mazarguil To: Moti Haimovsky Cc: dev@dpdk.org Message-ID: <20180105165317.GV4256@6wind.com> References: <1515082323-179525-1-git-send-email-motih@mellanox.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1515082323-179525-1-git-send-email-motih@mellanox.com> Subject: Re: [dpdk-dev] [PATCH] net/mlx4: verify Tx max sges X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 05 Jan 2018 16:53:29 -0000 On Thu, Jan 04, 2018 at 06:12:03PM +0200, Moti Haimovsky wrote: > Max number of Tx scatter-gather entries is a property of the device > and is queried at init. This value was not changed in a while and > most probably will not be changed in the future, Therefore and > in order to enhance Tx performance, the Tx max-sge value is hardcoded > in mlx4 PRM code. > This patch adds a verification that the above assumption still holds > and that the hardcoded value is still supported by the mlx4 hardware. > > Signed-off-by: Moti Haimovsky Except for a really minor nit below: Acked-by: Adrien Mazarguil > --- > drivers/net/mlx4/mlx4.c | 1 + > drivers/net/mlx4/mlx4_prm.h | 5 ++++- > 2 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/mlx4/mlx4.c b/drivers/net/mlx4/mlx4.c > index 4bc4a6f..61c5bf4 100644 > --- a/drivers/net/mlx4/mlx4.c > +++ b/drivers/net/mlx4/mlx4.c > @@ -505,6 +505,7 @@ struct mlx4_conf { > rte_errno = ENODEV; > goto error; > } > + assert(device_attr.max_sge >= MLX4_MAX_SGE); > for (i = 0; i < device_attr.phys_port_cnt; i++) { > uint32_t port = i + 1; /* ports are indexed from one */ > struct ibv_context *ctx = NULL; > diff --git a/drivers/net/mlx4/mlx4_prm.h b/drivers/net/mlx4/mlx4_prm.h > index 217ea50..b382d59 100644 > --- a/drivers/net/mlx4/mlx4_prm.h > +++ b/drivers/net/mlx4/mlx4_prm.h > @@ -53,7 +53,10 @@ > #define MLX4_TXBB_SIZE (1 << MLX4_TXBB_SHIFT) > > /* Typical TSO descriptor with 16 gather entries is 352 bytes. */ > -#define MLX4_MAX_WQE_SIZE 512 > +#define MLX4_MAX_SGE 32 > +#define MLX4_MAX_WQE_SIZE \ > + (MLX4_MAX_SGE * sizeof(struct mlx4_wqe_data_seg) + \ > + sizeof(struct mlx4_wqe_ctrl_seg)) One extra indent space is needed before sizeof to align with parenthesis contents. -- Adrien Mazarguil 6WIND