From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR01-VE1-obe.outbound.protection.outlook.com (mail-ve1eur01on0072.outbound.protection.outlook.com [104.47.1.72]) by dpdk.org (Postfix) with ESMTP id CBEF7199AC for ; Thu, 25 Jan 2018 22:03:11 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=xtIvv6rlX8QHSr6aPXVAep5vcLB9asV3n1RRderCuOc=; b=bf0PIpxtVKV0B2zTgqFfjeMZR4HTX3g2N1ibtgCSHqNTS8mT8YiFqOoSqAuhpPjGZgb1ImTU8yXrkNxRj1Jc5TM41VYthx5okNwU3oZUfFc8J/KxJxBvl1QlGFnDknd7WXcy/36W+3BcSvISPKOXbrjakX8vTX7E39H54Rkonq4= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; Received: from mellanox.com (209.116.155.178) by DB6PR0501MB2037.eurprd05.prod.outlook.com (2603:10a6:4:6::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.444.14; Thu, 25 Jan 2018 21:03:05 +0000 From: Yongseok Koh To: adrien.mazarguil@6wind.com, nelio.laranjeiro@6wind.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, chaozhu@linux.vnet.ibm.com, jerin.jacob@caviumnetworks.com, jianbo.liu@arm.com Cc: arybchenko@solarflare.com, dev@dpdk.org, Yongseok Koh Date: Thu, 25 Jan 2018 13:02:41 -0800 Message-Id: <20180125210250.38233-1-yskoh@mellanox.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180119004430.15305-1-yskoh@mellanox.com> References: <20180119004430.15305-1-yskoh@mellanox.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [209.116.155.178] X-ClientProxiedBy: CY4PR15CA0014.namprd15.prod.outlook.com (2603:10b6:910:14::24) To DB6PR0501MB2037.eurprd05.prod.outlook.com (2603:10a6:4:6::19) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 4eee67c3-2b72-48c6-5eeb-08d5643708a7 X-Microsoft-Antispam: UriScan:; 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DB6PR0501MB2037; 6:+OIKYra3YpDYhMk8D4EYmkjEhTgcemaDF0+Fiq2Mq3Qj4R8zXTmTytZckwvctd1n+9aK9KFNter5ddII83k8/YZWfCHe+COJCfmdEWopgk+z9r/mF2yGIwfK9Hplr/fqkxX2SPfXFRvbqZaL9+Hx/Vt6+F6fEOHkEoy1z7z/mqzVkpAG/XkHjwsnFbkmFgHzWQ0ZwdlmA2SDjr0wKyTMvebFOr4Ul18FaOFgj+NtFixNCq3FGvBM7/cod3E0TVd1GvZu/NxkQwfr976C9DxtVjlTNsAkfuUUTY2faBjoebN8qnWCctVp9Ik3RHZ7YuOqarc/5N5FiII/xap3lj3sabBWGZhrzvEjyEM/I3h9rKw=; 5:4eqCpdWrtTzm+5jg9lnH5gEsw7rszOfB5V5gAbRnI3tk6Bt+uN7LUk96L+rfaBIwpXBaDaQUzHs8RHbYl5lRb4mIo78793qUpGPjRBUucKw6rx6Gx7Ck0siZr9Nfc88RD8RaCzSsEKUbLDrPgciF6unT4hKK5DLh1cO/ZZ5hc9o=; 24:bkmLDyYsqPiph4id2MFTnlVxSAQwXt8+vJW9VWpZ+QZ3HwDLXckIlXC+bnOTS8Sy4VXWp2nfX4RlK5RVRcTh+JNNfBe4Z3p7+YdbH8LER4k=; 7:c67at7ANG1JIk5jo29zQ5FPSBhGEKAkxYO8Tvzq6Eyk6x+EVzeFQ4x6Cq+HXBwV8l1jVkcK/TtYYDRtFdbj7SQQUmJdneh9oO3i4cz23/RitAeM5mqUE+lU+Uh2FWzo4fpzco9b/DhORyDjIeq4n0WajOg8hQPcbugyryyQG4Yr72pPWxtIF6CLznxfQRJTPtNRUMB+1BqkHuIyI/5wHZf7DkrYVv7kFkur8gLohXqYR+Z5UI0zi4VA3Gp825UnZ SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jan 2018 21:03:05.6145 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4eee67c3-2b72-48c6-5eeb-08d5643708a7 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0501MB2037 Subject: [dpdk-dev] [PATCH v4 0/9] introduce coherent I/O memory barriers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 25 Jan 2018 21:03:12 -0000 This patchset is to introduce coherent I/O memory barriers, which could be more efficient for coherent memory between I/O device and CPU, especially for ARMv8. v4: * rename barriers to "coherent I/O memory barrier". * Make groups for various barriers in Doxygen doc. v3: * add more detailed comments about the new memory barriers. v2: * introduce DMA memory barriers. Yongseok Koh (9): eal: add Doxygen grouping for memory barriers eal: introduce coherent I/O memory barriers eal/x86: define coherent I/O memory barriers eal/ppc64: define coherent I/O memory barriers eal/armv7: define coherent I/O memory barriers eal/arm64: define coherent I/O memory barriers net/mlx5: remove unnecessary memory barrier net/mlx5: replace I/O memory barrier with coherent version net/mlx5: fix synchronization on polling Rx completions drivers/net/mlx5/mlx5_rxq.c | 1 - drivers/net/mlx5/mlx5_rxtx.c | 5 +- drivers/net/mlx5/mlx5_rxtx.h | 2 +- drivers/net/mlx5/mlx5_rxtx_vec.h | 2 +- drivers/net/mlx5/mlx5_rxtx_vec_neon.h | 53 ++++++++++++---------- drivers/net/mlx5/mlx5_rxtx_vec_sse.h | 2 +- .../common/include/arch/arm/rte_atomic_32.h | 4 ++ .../common/include/arch/arm/rte_atomic_64.h | 4 ++ .../common/include/arch/ppc_64/rte_atomic.h | 4 ++ .../common/include/arch/x86/rte_atomic.h | 4 ++ lib/librte_eal/common/include/generic/rte_atomic.h | 51 +++++++++++++++++++++ 11 files changed, 103 insertions(+), 29 deletions(-) -- 2.11.0