From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 8FE252BF3 for ; Thu, 1 Feb 2018 10:59:39 +0100 (CET) X-Amp-Result: UNSCANNABLE X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Feb 2018 01:59:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,443,1511856000"; d="scan'208";a="197839129" Received: from bricha3-mobl3.ger.corp.intel.com ([10.237.221.77]) by orsmga005.jf.intel.com with SMTP; 01 Feb 2018 01:59:36 -0800 Received: by (sSMTP sendmail emulation); Thu, 01 Feb 2018 09:59:35 +0000 Date: Thu, 1 Feb 2018 09:59:35 +0000 From: Bruce Richardson To: Changpeng Liu Cc: dev@dpdk.org, ferruh.yigit@intel.com Message-ID: <20180201095934.GA13452@bricha3-MOBL3.ger.corp.intel.com> References: <1517447902-4166-1-git-send-email-changpeng.liu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1517447902-4166-1-git-send-email-changpeng.liu@intel.com> Organization: Intel Research and Development Ireland Ltd. User-Agent: Mutt/1.9.1 (2017-09-22) Subject: Re: [dpdk-dev] [PATCH] pci/uio: enable prefetchable resources mapping X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 01 Feb 2018 09:59:39 -0000 On Thu, Feb 01, 2018 at 09:18:22AM +0800, Changpeng Liu wrote: > For PCI prefetchable resources, Linux will create a > write combined file as well, the library will try > to map resourceX_wc file first, if the file does > not exist, then it will map resourceX as usual. > > Signed-off-by: Changpeng Liu > --- > drivers/bus/pci/linux/pci_uio.c | 19 ++++++++++++++----- > 1 file changed, 14 insertions(+), 5 deletions(-) > Hi, Given the lack of ordering guarantees with write-combined memory, I would have thought that this is very risky to do without a complete set of changes inside the PMDs to add in the necessary memory barriers to ensure ordering of operations to the BARs. Therefore, instead of mapping one file or another, I think the change should be made to map *both* in DPDK if available. Then each driver can chose whether to write a given device register using uncacheable memory type or write-combining memory type + any appropriate barriers. For example, with many NICs the initialization of the device involves many register writes in a pretty defined order, so wc operations are probably to suitable as performance is not a concern. However, for data path operations, a driver may chose to use wc memory for the occasional device writes there, for performance reasons. Regards, /Bruce