From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM01-BN3-obe.outbound.protection.outlook.com (mail-bn3nam01on0082.outbound.protection.outlook.com [104.47.33.82]) by dpdk.org (Postfix) with ESMTP id 0E3371B6AE for ; Tue, 6 Feb 2018 07:03:15 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=G33on1ShUb8iANZhMa3MtzQf8NgfOd7AZTlVKzCLVOU=; b=i0Eop9o8xyELsEQs+hvD4XmV/UqVEZAFPZmll/BLeR75wjhxIrSeV8yvih1b5n8tkryG58nJs7N1bmtBR9vHeWqwiwdvBa1KjeZKi+RxY8h9oeRpI/6uIr0HGDHck4xepgPecklQQle9mn4exFEvSrD8MK068/6O0obKl6FYhqQ= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Pavan.Bhagavatula@cavium.com; Received: from Pavan-LT (111.93.218.67) by MWHPR07MB3472.namprd07.prod.outlook.com (10.164.192.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.464.11; Tue, 6 Feb 2018 06:03:10 +0000 Date: Tue, 6 Feb 2018 11:32:59 +0530 From: Pavan Nikhilesh To: Herbert Guan , "jerin.jacob@caviumnetworks.com" , "hemant.agrawal@nxp.com" , "bruce.richardson@intel.com" , "harry.van.haaren@intel.com" Cc: dev@dpdk.org Message-ID: <20180206060257.rwr4jhtdlc72f33l@Pavan-LT> References: <1517375549-29756-1-git-send-email-herbert.guan@arm.com> <1517384359-1438-1-git-send-email-herbert.guan@arm.com> <20180205092244.yf34vqtvvwu6djfz@Pavan-LT> MIME-Version: 1.0 Content-Type: text/plain; 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MWHPR07MB3472; 6:HNa2HU3+aez5sdVyTBzfMDzjz+HZa/wVxgBdBrkZ1hAy91kP57R5wEijk4kYoQG42tK3tUfh54aeyEiB1+KxReQhi+Ri7AG2D5FQpPnMs45HYcG8ogiTAb712FAGVYE/qdHrbjgeygh7V33px0svJDqYp8JQnN8pIEHXaW4SgbZZSd/bmVHsLL24jq7RTkX5cv8oCS4wtdODMevzJYlfcCtD2ZfJs+UZqoqVo8IYfEGypwb82dVa4skSdN9m29a3Mzf6U74xAYW1pMFPXRG64Zp3qjsQ5yzUQdJFNRC5lxirBRX6JR9wHFPGTc2uwbgrI2dAxjuZTw7Y1hBms/1wCcv9Y0ojJfu2eNXSa6Bk1po=; 5:oMOya+jft2jslv692HpU1PZcKgp6iXwERG5kfOcfiRomFWq/lX4DXZEuKL5vAtHls2KqAp8LZXY4/xihPLxKItHabNImOtoPbztTusrfa3CZQ/FQrf1LVLIIth7+z2wWOWZ7Rxe3C9OOuboBfR9wwq2J5ehKfgwSKja3SqgwzHc=; 24:T3W2GPqy+piAKT6JmDm643mPwcZ8+VTubsky0IsVVWFIWG6MWFYma0CYVuviXkwNvkwYd/tl7hqnGCXrofC30kLfWZwaElCM0dpJko9GA9M=; 7:Z/NmgsHWNyoOoB5TsoWOVZNOWpDg3hbLv8N+xOS9PzE7qAY0+GbDMzmzUKnBOk0lUIRXQh6i1kkiwIyPP2iYp2OURiORT7Y5ctDLj+llj6ILrWst/fgLuY7FSjG8LSMzySrwhRXPl1K/nCKDGlDdPnuwfO0UEukV6+OxLTTbKzfHa3HvVGMElteCfNX02Hp4e6pnJwKwtp3UtIbTJrAwBuV+bJ3f1qKdJzMe+i7lv17pilYEIWCWhVPAPCAKXfwD SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Feb 2018 06:03:10.9015 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 44a2646c-97b3-4114-21e7-08d56d274e59 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 711e4ccf-2e9b-4bcf-a551-4094005b6194 X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR07MB3472 Subject: Re: [dpdk-dev] [PATCH v1] build: add more implementers' IDs and PNs for Arm platforms X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 06 Feb 2018 06:03:15 -0000 On Tue, Feb 06, 2018 at 05:51:29AM +0000, Herbert Guan wrote: > Hi Pavan, > > > -----Original Message----- > > From: Pavan Nikhilesh [mailto:pbhagavatula@caviumnetworks.com] > > Sent: Monday, February 5, 2018 17:23 > > To: Herbert Guan ; > > jerin.jacob@caviumnetworks.com; hemant.agrawal@nxp.com; > > bruce.richardson@intel.com; harry.van.haaren@intel.com > > Cc: dev@dpdk.org > > Subject: Re: [PATCH v1] build: add more implementers' IDs and PNs for Arm > > platforms > > > > Hi Herbert, > > > > On Wed, Jan 31, 2018 at 03:39:19PM +0800, Herbert Guan wrote: > > > 1) Add native PN option '-march=native' to allow automatic detection. > > > Set 'arm_force_native_march' to 'true' in config/arm/meson.build > > > to use native PN option. > > > 2) Add implementer_pn option for part num selection in cross compile > > > 3) Add known Arm cortex PN support > > > 4) Add known implementers' IDs (use generic flags/archs by default) > > > 5) Sync build options with config/common_armv8a_linuxapp > > > > > > Signed-off-by: Herbert Guan > > > --- > > > > > + > > > machine_args_generic = [ > > > -['default', ['-march=armv8-a+crc+crypto']]] > > > +['default', ['-march=armv8-a']], > > > > Any specific reason for this change? > > Traditional make uses > > MACHINE_CFLAGS += -march=armv8-a+crc+crypto > > found at mk/machine/armv8a/rte.vars.mk > > > > Both CRC and Crypto are optional instructions / extensions on Arm v8 CPUs. > When making a general build (e.g. a release build for distribution), we need to > ensure all targeted CPUs (all Armv8 for example) can support this compiled > binary. Defaulting crc and crypto to be supported may introduce risks. For a certain > CPU/platform, '-march=native' may be used, or CPU implementers can further > Customize these args in this file. > On the other hand, the rte_cpuflags.c is already supporting run-time CPU flags > (instruction sets) detection and this is the preferred approach. > Makes sense, As I mentioned in the previous mail some vendors use 64B cacheline instead of 128B as of now I dont see a way to detect that. The vendor needs to modify implementor Id specific flags flags_. With that in mind. Acked-by: Pavan Nikhilesh