From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 2FD791B7C5 for ; Thu, 8 Feb 2018 09:45:06 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Feb 2018 00:45:05 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,477,1511856000"; d="scan'208";a="202283661" Received: from dpdk2.bj.intel.com ([172.16.182.81]) by fmsmga005.fm.intel.com with ESMTP; 08 Feb 2018 00:45:04 -0800 From: Wei Zhao To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Wei Zhao Date: Thu, 8 Feb 2018 16:36:30 +0800 Message-Id: <20180208083630.103388-3-wei.zhao1@intel.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20180208083630.103388-1-wei.zhao1@intel.com> References: <20180208083630.103388-1-wei.zhao1@intel.com> Subject: [dpdk-dev] [PATCH 2/2] net/fm10k: add support for check descriptor status APIs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Feb 2018 08:45:06 -0000 Fm10k nic need to support check descriptor status APIs, they are rte_eth_rx_descriptor_status and rte_eth_tx_descriptor_status. So, this patch add ops with function pointer that enable feature. Signed-off-by: Wei Zhao --- drivers/net/fm10k/fm10k.h | 7 +++++ drivers/net/fm10k/fm10k_ethdev.c | 2 ++ drivers/net/fm10k/fm10k_rxtx.c | 65 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 74 insertions(+) diff --git a/drivers/net/fm10k/fm10k.h b/drivers/net/fm10k/fm10k.h index 30dad3e..65dc0bd 100644 --- a/drivers/net/fm10k/fm10k.h +++ b/drivers/net/fm10k/fm10k.h @@ -328,6 +328,13 @@ uint16_t fm10k_recv_scattered_pkts(void *rx_queue, int fm10k_dev_rx_descriptor_done(void *rx_queue, uint16_t offset); +int +fm10k_dev_rx_descriptor_status(void *rx_queue, uint16_t offset); + +int +fm10k_dev_tx_descriptor_status(void *rx_queue, uint16_t offset); + + uint16_t fm10k_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts); diff --git a/drivers/net/fm10k/fm10k_ethdev.c b/drivers/net/fm10k/fm10k_ethdev.c index 9423761..9293828 100644 --- a/drivers/net/fm10k/fm10k_ethdev.c +++ b/drivers/net/fm10k/fm10k_ethdev.c @@ -2784,6 +2784,8 @@ static const struct eth_dev_ops fm10k_eth_dev_ops = { .tx_queue_setup = fm10k_tx_queue_setup, .tx_queue_release = fm10k_tx_queue_release, .rx_descriptor_done = fm10k_dev_rx_descriptor_done, + .rx_descriptor_status = fm10k_dev_rx_descriptor_status, + .tx_descriptor_status = fm10k_dev_tx_descriptor_status, .rx_queue_intr_enable = fm10k_dev_rx_queue_intr_enable, .rx_queue_intr_disable = fm10k_dev_rx_queue_intr_disable, .reta_update = fm10k_reta_update, diff --git a/drivers/net/fm10k/fm10k_rxtx.c b/drivers/net/fm10k/fm10k_rxtx.c index 9320748..fa4f028 100644 --- a/drivers/net/fm10k/fm10k_rxtx.c +++ b/drivers/net/fm10k/fm10k_rxtx.c @@ -389,6 +389,71 @@ fm10k_dev_rx_descriptor_done(void *rx_queue, uint16_t offset) return ret; } +int +fm10k_dev_rx_descriptor_status(void *rx_queue, uint16_t offset) +{ + volatile union fm10k_rx_desc *rxdp; + struct fm10k_rx_queue *rxq = rx_queue; + uint16_t nb_hold, trigger_last; + uint16_t desc; + int ret; + + if (unlikely(offset >= rxq->nb_desc)) { + PMD_DRV_LOG(ERR, "Invalid RX descriptor offset %u", offset); + return 0; + } + + if (rxq->next_trigger < rxq->alloc_thresh) + trigger_last = rxq->next_trigger + + rxq->nb_desc - rxq->alloc_thresh; + else + trigger_last = rxq->next_trigger - rxq->alloc_thresh; + + if (rxq->next_dd < trigger_last) + nb_hold = rxq->next_dd + rxq->nb_desc - trigger_last; + else + nb_hold = rxq->next_dd - trigger_last; + + if (offset >= rxq->nb_desc - nb_hold) + return RTE_ETH_RX_DESC_UNAVAIL; + + desc = rxq->next_dd + offset; + if (desc >= rxq->nb_desc) + desc -= rxq->nb_desc; + + rxdp = &rxq->hw_ring[desc]; + + ret = !!(rxdp->w.status & + rte_cpu_to_le_16(FM10K_RXD_STATUS_DD)); + + return ret; +} + +int +fm10k_dev_tx_descriptor_status(void *tx_queue, uint16_t offset) +{ + volatile struct fm10k_tx_desc *txdp; + struct fm10k_tx_queue *txq = tx_queue; + uint16_t desc; + int ret; + + if (unlikely(offset >= txq->nb_desc)) { + PMD_DRV_LOG(ERR, "Invalid TX descriptor offset %u", offset); + return 0; + } + + desc = txq->next_dd + offset; + if (desc >= txq->nb_desc) + desc -= txq->nb_desc; + + txdp = &txq->hw_ring[desc]; + + ret = !!(txdp->flags & + rte_cpu_to_le_16(FM10K_TXD_FLAG_DONE)); + + return ret; +} + /* * Free multiple TX mbuf at a time if they are in the same pool * -- 2.9.3