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DM5PR07MB3467; 6:KPBsFjjQxs47rz0ZGlb4NZzUJ5m0vLujYRD4Y8uTLeJlMXR1CO13LCPE0riRijDU+cGPMHqpoPeJTcsmwt62XUGG2BXm1JtyER+chzz9NqdDqKzn8Ek6ehbtK0GDV71I3MVsyn5Efme6cIMq8Wmly6KuS4SE8HNPI3IJD1MnKs7lEHJAdAKeCLFqAuqw+7Vz4Z9+4+7hAEzeO6/XNX2HSHcj3LT2KAVOUR/KejTvEOSdhA1oOISY2TKqMNAxcLrI3zk6XWqU3q05sOIiwGexXMkjUP5EOVyUva8vxEZBuUVc9HyCrgs0Nvu+wB1wBYpwTzsSV3M0NPoUSnW0U39ijviFrOTsm7ZGO70weNaVbhQ=; 5:QjK8A7zrairGuZ10txIgGivUe2HFEVue9EdjbZ/yqFeCkL8yx9t91pPic8xvXh7Qr1RR44InRyjV/+qEUcOaGWyocXfyNIKLbHgHmMpPgV1skm4UCO6s2RZIzMnxaq3Qs8OaHecM/um4SsnLdcNGbV5UI6H9TzB9mjgPGul/lTw=; 24:XxtCHcMI+BwpfiTu3DJ08k0224VTyD1rlMFSsS2A/52f213cWJoQ7TwXjLeCOFeM1ELXU32aKlPzSkqgEGJjMhvifrxD6R7tjA+d6/JokzE=; 7:dkjKvQBkJouQrGT2WOT3yPfLt4JjF0mOixtATWWxgqv+nQyqXE8CB09PoukopkMfqCuUkoQEnTOVVhth1TwZoC1wZk43cjE9IAU60N0y9Mi7Ja3CRqv8b/5XkmB5oBWNlLe16EPwGOcXYuq6VxyascADQrCA+AgaFLwwN93jbg6U4qqmSczgq4b/cprLfuQGZSS07uVIbSS1+40/JsvdUNgDAXIIrJ6TO1wKsncXGvYw0gLMVoTlaMDyF/XZKWgn SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Feb 2018 21:37:39.4901 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1167decd-2390-4446-15cf-08d5758581ea X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 711e4ccf-2e9b-4bcf-a551-4094005b6194 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR07MB3467 Subject: [dpdk-dev] [PATCH 03/10] event/octeontx: add support to create and free timer adapter X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Feb 2018 21:37:43 -0000 When the application requests to create a timer device, Octeontx TIM create does the following: - Get the requested TIMvf ring based on adapter_id. - Verify the config parameters supplied. - Allocate memory required for * Buckets based on min and max timeout supplied. * Allocate the chunk pool based on the number of timers. - Clear the interrupts. On Free: - Free the allocated bucket and chunk memory. - Free private data used by TIMvf. Signed-off-by: Pavan Nikhilesh --- drivers/event/octeontx/Makefile | 1 + drivers/event/octeontx/meson.build | 3 +- drivers/event/octeontx/ssovf_evdev.c | 3 + drivers/event/octeontx/timvf_evdev.c | 160 +++++++++++++++++++++++++++++++++++ drivers/event/octeontx/timvf_evdev.h | 158 ++++++++++++++++++++++++++++++++++ 5 files changed, 324 insertions(+), 1 deletion(-) create mode 100644 drivers/event/octeontx/timvf_evdev.c create mode 100644 drivers/event/octeontx/timvf_evdev.h diff --git a/drivers/event/octeontx/Makefile b/drivers/event/octeontx/Makefile index 0e49efd84..f1d10a99e 100644 --- a/drivers/event/octeontx/Makefile +++ b/drivers/event/octeontx/Makefile @@ -27,6 +27,7 @@ LIBABIVER := 1 SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF) += ssovf_worker.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF) += ssovf_evdev.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF) += ssovf_evdev_selftest.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF) += timvf_evdev.c ifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y) CFLAGS_ssovf_worker.o += -fno-prefetch-loop-arrays diff --git a/drivers/event/octeontx/meson.build b/drivers/event/octeontx/meson.build index 358fc9fc9..8941f8a56 100644 --- a/drivers/event/octeontx/meson.build +++ b/drivers/event/octeontx/meson.build @@ -3,7 +3,8 @@ sources = files('ssovf_worker.c', 'ssovf_evdev.c', - 'ssovf_evdev_selftest.c' + 'ssovf_evdev_selftest.c', + 'timvf_evdev.c', ) deps += ['mempool_octeontx', 'bus_vdev', 'pmd_octeontx'] diff --git a/drivers/event/octeontx/ssovf_evdev.c b/drivers/event/octeontx/ssovf_evdev.c index a1086077d..54384d465 100644 --- a/drivers/event/octeontx/ssovf_evdev.c +++ b/drivers/event/octeontx/ssovf_evdev.c @@ -18,6 +18,7 @@ #include #include "ssovf_evdev.h" +#include "timvf_evdev.h" int otx_logtype_ssovf; @@ -610,6 +611,8 @@ static const struct rte_eventdev_ops ssovf_ops = { .eth_rx_adapter_start = ssovf_eth_rx_adapter_start, .eth_rx_adapter_stop = ssovf_eth_rx_adapter_stop, + .timer_adapter_caps_get = timvf_timer_adapter_caps_get, + .dev_selftest = test_eventdev_octeontx, .dump = ssovf_dump, diff --git a/drivers/event/octeontx/timvf_evdev.c b/drivers/event/octeontx/timvf_evdev.c new file mode 100644 index 000000000..a56ca7e71 --- /dev/null +++ b/drivers/event/octeontx/timvf_evdev.c @@ -0,0 +1,160 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Cavium, Inc + */ + +#include "timvf_evdev.h" + +int otx_logtype_timvf; + +RTE_INIT(otx_timvf_init_log); +static void +otx_timvf_init_log(void) +{ + otx_logtype_timvf = rte_log_register("pmd.event.octeontx.timer"); + if (otx_logtype_timvf >= 0) + rte_log_set_level(otx_logtype_timvf, RTE_LOG_NOTICE); +} + +static void +timvf_ring_info_get(const struct rte_event_timer_adapter *adptr, + struct rte_event_timer_adapter_info *adptr_info) +{ + struct timvf_ring *timr = adptr->data->adapter_priv; + adptr_info->max_tmo_ns = timr->max_tout; + adptr_info->min_resolution_ns = timr->tck_nsec; + rte_memcpy(&adptr_info->conf, &adptr->data->conf, + sizeof(struct rte_event_timer_adapter_conf)); +} + +static int +timvf_ring_create(struct rte_event_timer_adapter *adptr) +{ + char pool_name[25]; + int ret; + uint64_t nb_timers; + struct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf; + struct timvf_ring *timr; + struct octeontx_timvf_info tinfo; + + if (octeontx_timvf_info(&tinfo) < 0) + return -ENODEV; + + if (adptr->data->id >= tinfo.total_timvfs) + return -ENODEV; + + timr = rte_zmalloc("octeontx_timvf_priv", + sizeof(struct timvf_ring), 0); + if (timr == NULL) + return -ENOMEM; + + adptr->data->adapter_priv = timr; + /* Check config parameters. */ + if ((rcfg->clk_src != RTE_EVENT_TIMER_ADAPTER_EXT_CLK0) && + (!rcfg->timer_tick_ns || + rcfg->timer_tick_ns < TIM_MIN_INTERVAL)) { + timvf_log_err("Too low timer ticks"); + goto cfg_err; + } + + switch (rcfg->clk_src) { + case RTE_EVENT_TIMER_ADAPTER_CPU_CLK: + timr->clk_src = TIM_CLK_SRC_SCLK; + break; + case RTE_EVENT_TIMER_ADAPTER_EXT_CLK0: + timr->clk_src = TIM_CLK_SRC_GPIO; + break; + case RTE_EVENT_TIMER_ADAPTER_EXT_CLK1: + timr->clk_src = TIM_CLK_SRC_GTI; + break; + case RTE_EVENT_TIMER_ADAPTER_EXT_CLK2: + timr->clk_src = TIM_CLK_SRC_PTP; + break; + default: + timvf_log_err("Invalid clk source specified."); + goto cfg_err; + } + + timr->tim_ring_id = adptr->data->id; + timr->tck_nsec = rcfg->timer_tick_ns; + timr->max_tout = rcfg->max_tmo_ns; + timr->meta.nb_bkts = (timr->max_tout / timr->tck_nsec) + 1; + timr->vbar0 = octeontx_timvf_bar(timr->tim_ring_id, 0); + timr->bkt_pos = (uint8_t *)timr->vbar0 + TIM_VRING_REL; + nb_timers = rcfg->nb_timers; + timr->meta.get_target_bkt = bkt_mod; + + timr->nb_chunks = nb_timers / nb_chunk_slots; + + timr->meta.bkt = rte_zmalloc("octeontx_timvf_bucket", + (timr->meta.nb_bkts) * sizeof(struct tim_mem_bucket), + 0); + if (timr->meta.bkt == NULL) + goto mem_err; + + snprintf(pool_name, 30, "timvf_meta.chunk_pool%d", timr->tim_ring_id); + timr->meta.chunk_pool = (void *)rte_mempool_create_empty(pool_name, + timr->nb_chunks, TIM_CHUNK_SIZE, 0, 0, rte_socket_id(), + 0); + + if (!timr->meta.chunk_pool) { + rte_free(timr->meta.bkt); + timvf_log_err("Unable to create chunkpool."); + return -ENOMEM; + } + + ret = rte_mempool_set_ops_byname(timr->meta.chunk_pool, + RTE_MBUF_DEFAULT_MEMPOOL_OPS, NULL); + timvf_log_dbg("Not giving back chunks to fpa"); + + if (ret != 0) { + timvf_log_err("Unable to set chunkpool ops."); + goto mem_err; + } + + ret = rte_mempool_populate_default(timr->meta.chunk_pool); + if (ret < 0) { + timvf_log_err("Unable to set populate chunkpool."); + goto mem_err; + } + timvf_write64(0, (uint8_t *)timr->vbar0 + TIM_VRING_BASE); + timvf_write64(0, (uint8_t *)timr->vbar0 + TIM_VF_NRSPERR_INT); + timvf_write64(0, (uint8_t *)timr->vbar0 + TIM_VF_NRSPERR_INT_W1S); + timvf_write64(0x7, (uint8_t *)timr->vbar0 + TIM_VF_NRSPERR_ENA_W1C); + timvf_write64(0x7, (uint8_t *)timr->vbar0 + TIM_VF_NRSPERR_ENA_W1S); + + return 0; +mem_err: + rte_free(timr); + return -ENOMEM; +cfg_err: + rte_free(timr); + return -EINVAL; +} + +static int +timvf_ring_free(struct rte_event_timer_adapter *adptr) +{ + struct timvf_ring *timr = adptr->data->adapter_priv; + rte_mempool_free(timr->meta.chunk_pool); + rte_free(timr->meta.bkt); + rte_free(adptr->data->adapter_priv); + return 0; +} + +static struct rte_event_timer_adapter_ops timvf_ops = { + .init = timvf_ring_create, + .uninit = timvf_ring_free, + .get_info = timvf_ring_info_get, +}; + +int +timvf_timer_adapter_caps_get(const struct rte_eventdev *dev, uint64_t flags, + uint32_t *caps, const struct rte_event_timer_adapter_ops **ops) +{ + RTE_SET_USED(dev); + RTE_SET_USED(flags); + *caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT; + *ops = &timvf_ops; + return -EINVAL; +} diff --git a/drivers/event/octeontx/timvf_evdev.h b/drivers/event/octeontx/timvf_evdev.h new file mode 100644 index 000000000..fcc938b82 --- /dev/null +++ b/drivers/event/octeontx/timvf_evdev.h @@ -0,0 +1,158 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Cavium, Inc + */ + +#ifndef __TIMVF_EVDEV_H__ +#define __TIMVF_EVDEV_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define timvf_log(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, otx_logtype_timvf, \ + "[%s] %s() " fmt "\n", \ + RTE_STR(event_timer_octeontx), __func__, ## args) + +#define timvf_log_info(fmt, ...) timvf_log(INFO, fmt, ##__VA_ARGS__) +#define timvf_log_dbg(fmt, ...) timvf_log(DEBUG, fmt, ##__VA_ARGS__) +#define timvf_log_err(fmt, ...) timvf_log(ERR, fmt, ##__VA_ARGS__) +#define timvf_func_trace timvf_log_dbg + +#define TIM_COPROC (8) +#define TIM_GET_DEV_INFO (1) +#define TIM_GET_RING_INFO (2) +#define TIM_SET_RING_INFO (3) +#define TIM_RING_START_CYC_GET (4) + +#define TIM_MAX_RINGS (64) +#define TIM_DEV_PER_NODE (1) +#define TIM_VF_PER_DEV (64) +#define TIM_RING_PER_DEV (TIM_VF_PER_DEV) +#define TIM_RING_NODE_SHIFT (6) +#define TIM_RING_MASK ((TIM_RING_PER_DEV) - 1) +#define TIM_RING_INVALID (-1) + +#define TIM_MIN_INTERVAL (1E3) +#define TIM_MAX_INTERVAL ((1ull << 32) - 1) +#define TIM_MAX_BUCKETS (1ull << 20) +#define TIM_CHUNK_SIZE (4096) +#define TIM_MAX_CHUNKS_PER_BUCKET (1ull << 32) + +#define TIMVF_MAX_BURST (8) + +/* TIM VF Control/Status registers (CSRs): */ +/* VF_BAR0: */ +#define TIM_VF_NRSPERR_INT (0x0) +#define TIM_VF_NRSPERR_INT_W1S (0x8) +#define TIM_VF_NRSPERR_ENA_W1C (0x10) +#define TIM_VF_NRSPERR_ENA_W1S (0x18) +#define TIM_VRING_FR_RN_CYCLES (0x20) +#define TIM_VRING_FR_RN_GPIOS (0x28) +#define TIM_VRING_FR_RN_GTI (0x30) +#define TIM_VRING_FR_RN_PTP (0x38) +#define TIM_VRING_CTL0 (0x40) +#define TIM_VRING_CTL1 (0x50) +#define TIM_VRING_CTL2 (0x60) +#define TIM_VRING_BASE (0x100) +#define TIM_VRING_AURA (0x108) +#define TIM_VRING_REL (0x110) + +#define timvf_read64 rte_read64_relaxed +#define timvf_write64 rte_write64_relaxed + +#ifndef __hot +#define __hot __attribute__((hot)) +#endif + +extern int otx_logtype_timvf; + +static const uint16_t nb_chunk_slots = (TIM_CHUNK_SIZE / 16) - 1; + +enum timvf_clk_src { + TIM_CLK_SRC_SCLK, + TIM_CLK_SRC_GPIO, + TIM_CLK_SRC_GTI, + TIM_CLK_SRC_PTP, +}; + +/* TIM_MEM_BUCKET */ +struct tim_mem_bucket { + uint64_t first_chunk; + union { + uint64_t w1; + struct { + uint32_t nb_entry; + uint8_t sbt:1; + uint8_t hbt:1; + uint8_t bsk:1; + uint8_t rsvd:5; + uint8_t lock; + int16_t chunk_remainder; + }; + }; + uint64_t current_chunk; + uint64_t pad; +} __rte_packed; + +struct tim_mem_entry { + uint64_t w0; + uint64_t wqe; +} __rte_packed; + +struct timvf_ctrl_reg { + uint64_t rctrl0; + uint64_t rctrl1; + uint64_t rctrl2; + uint8_t use_pmu; +} __rte_packed; + +typedef uint32_t (*bkt_id)(uint32_t bkt_tcks, uint32_t nb_bkts); + +struct timvf_meta { + bkt_id get_target_bkt; + struct rte_reciprocal_u64 fast_div; + uint64_t ring_start_cyc; + uint32_t nb_bkts; + struct tim_mem_bucket *bkt; + void *chunk_pool; + uint64_t tck_int; +} __rte_cache_aligned; + +struct timvf_ring { + struct timvf_meta meta; + uint64_t tck_nsec; + void *vbar0; + void *bkt_pos; + uint64_t max_tout; + uint64_t nb_chunks; + enum timvf_clk_src clk_src; + uint16_t tim_ring_id; +} __rte_cache_aligned; + +static __rte_always_inline uint32_t __hot +bkt_mod(uint32_t rel_bkt, uint32_t nb_bkts) +{ + return rel_bkt % nb_bkts; +} + +int timvf_timer_adapter_caps_get(const struct rte_eventdev *dev, uint64_t flags, + uint32_t *caps, const struct rte_event_timer_adapter_ops **ops); + +#endif /* __TIMVF_EVDEV_H__ */ -- 2.16.1