From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 17FDE4C8E for ; Tue, 6 Mar 2018 12:36:27 +0100 (CET) X-Amp-Result: UNSCANNABLE X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Mar 2018 03:36:25 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.47,431,1515484800"; d="scan'208";a="36343972" Received: from bricha3-mobl3.ger.corp.intel.com ([10.237.221.36]) by orsmga001.jf.intel.com with SMTP; 06 Mar 2018 03:36:21 -0800 Received: by (sSMTP sendmail emulation); Tue, 06 Mar 2018 11:36:17 +0000 Date: Tue, 6 Mar 2018 11:36:17 +0000 From: Bruce Richardson To: =?iso-8859-1?Q?Ga=EBtan?= Rivet Cc: "Xu, Rosen" , Shreyansh Jain , "dev@dpdk.org" , "Doherty, Declan" , "Zhang, Tianfei" Message-ID: <20180306113616.GA7644@bricha3-MOBL3.ger.corp.intel.com> References: <1520300638-134954-1-git-send-email-rosen.xu@intel.com> <1520300638-134954-4-git-send-email-rosen.xu@intel.com> <0E78D399C70DA940A335608C6ED296D739F0ED23@SHSMSX104.ccr.corp.intel.com> <20180306104622.3ngsn6syickaphbm@bidouze.vm.6wind.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20180306104622.3ngsn6syickaphbm@bidouze.vm.6wind.com> Organization: Intel Research and Development Ireland Ltd. User-Agent: Mutt/1.9.3 (2018-01-21) Subject: Re: [dpdk-dev] [RFC 3/4] lib/librte_eal/common: Add Intel FPGA Bus Second Scan, it should be scanned after PCI Bus X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 06 Mar 2018 11:36:28 -0000 On Tue, Mar 06, 2018 at 11:46:22AM +0100, Gaëtan Rivet wrote: > On Tue, Mar 06, 2018 at 10:42:14AM +0000, Xu, Rosen wrote: > > > > > > -----Original Message----- > > From: Shreyansh Jain [mailto:shreyansh.jain@nxp.com] > > Sent: Tuesday, March 06, 2018 14:20 > > To: Xu, Rosen > > Cc: dev@dpdk.org; Doherty, Declan ; Zhang, Tianfei > > Subject: Re: [dpdk-dev] [RFC 3/4] lib/librte_eal/common: Add Intel FPGA Bus Second Scan, it should be scanned after PCI Bus > > > > On Tue, Mar 6, 2018 at 7:13 AM, Rosen Xu wrote: > > > Signed-off-by: Rosen Xu > > > --- > > > lib/librte_eal/common/eal_common_bus.c | 14 +++++++++++++- > > > 1 file changed, 13 insertions(+), 1 deletion(-) > > > > > > diff --git a/lib/librte_eal/common/eal_common_bus.c > > > b/lib/librte_eal/common/eal_common_bus.c > > > index 3e022d5..74bfa15 100644 > > > --- a/lib/librte_eal/common/eal_common_bus.c > > > +++ b/lib/librte_eal/common/eal_common_bus.c > > > @@ -70,15 +70,27 @@ struct rte_bus_list rte_bus_list = > > > rte_bus_scan(void) > > > { > > > int ret; > > > - struct rte_bus *bus = NULL; > > > + struct rte_bus *bus = NULL, *ifpga_bus = NULL; > > > > > > TAILQ_FOREACH(bus, &rte_bus_list, next) { > > > + if (!strcmp(bus->name, "ifpga")) { > > > + ifpga_bus = bus; > > > + continue; > > > + } > > > + > > > ret = bus->scan(); > > > if (ret) > > > RTE_LOG(ERR, EAL, "Scan for (%s) bus failed.\n", > > > bus->name); > > > } > > > > > > + if (ifpga_bus) { > > > + ret = ifpga_bus->scan(); > > > + if (ret) > > > + RTE_LOG(ERR, EAL, "Scan for (%s) bus failed.\n", > > > + ifpga_bus->name); > > > + } > > > + > > > > You are doing this just so that PCI scans are completed *before* ifpga scans? > > Rosen: yes > > Well, I understand that this certainly is an issue that we can't yet define a priority ordering of bus scans. > > > > But, I think what you are require is a simpler: > > > > In the file ifpga_bus.c: > > > > +RTE_REGISTER_BUS(IFPGA_BUS_NAME, rte_ifpga_bus.bus); <== this > > ... > > ... > > #define RTE_REGISTER_BUS(nm, bus) \ > > RTE_INIT_PRIO(businitfn_ ##nm, 110); \ > > > > If you define your own version of RTE_REGISTER_BUS with the priority number higher, it would be inserted later in the bus list. > > rte_register_bus doesn't do any inherent ordering. > > This would save the changes you are doing in the lib/librte_eal/common/eal_common_bus.c file. > > > > But I think there has to be a better provision of defining priority of bus scans - I am sure when new devices come in, there would be possibility of dependencies as in your case. > > Rosen: is the priority scan of bus is implemented? > > No, there is no priority set for scanning order. > However, the order in which buses are registered, will modify the order > in which scans are done. > > Thus, if you change the priority of your registration, you should be > able to ensure that your scan comes last. > Can we register the bus only when a PCI device match is found at runtime, e.g. as part of the PCI driver instance initialization? /Bruce